• A9 Code after vector table

    josecm
    josecm

    I am implementing a small OS as a university project in a A9 chip (a Xilinx Zynq). I am using trustzone to implement some features and I want to pass through SVC calls from user mode directly to monitor, so I issue an SMC in my SVC handler. Here it is…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Disabling L2 cache for CPU1 (Zynq-7000)

    irie
    irie

    Hello people,

    we are trying to make AMP application on Zynq 7000 custom board. We have a FreeRTOS v8.2.3 and lwIP v1.4.1 running on CPU0, while baremetal application is running on CPU1 and this one handles DMA configurations and its interrupts. We have…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex-A9 Preload and Lock Code in L2C-310

    josecm
    josecm

    I've been studying and experimenting with the caches on an ARM Cortex-A9, namely a Zynq SoC, for the past week with the main objective of loading and locking part of my code to L2 (PL310). The steps I take to achieve this are:

    • Set TTBR0 and Invalidate…
    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Porting code From Cortex-A9 to Cortex-R7

    Ajeesh
    Ajeesh

    Hi,

     

    I have some bare metal code written for Arm cortex A9. I would like to port this code to cortex R7. Since both of them belong to ARMv7, How much effort will this take?

    I have never worked on cortex R processors. Will i be able to use the same assembly…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Processor Modes in cortex-A57

    Ajeesh
    Ajeesh

    Hi,

    I have done some basic assembly in Armv7-A processors (cortex A9). The version of ARM supports modes like User, sys, SVC etc. Does the ARMv8 also has the similar modes? Where can i find the details. Please point me to the documents if any.

    Regards…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Porting code from Cortex-A9 to Cortex-A57

    Ajeesh
    Ajeesh

    Hi,

    I have been using I.MX6Q Sabre sd board (cortex-a9 ). I build image with my own start script and ld script. The image was loaded with u-boot. Now i would like to do the Same with Renesas R-Car M3(cortex A-57). How would i go about this? Can i use the…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is it possible at all to inspect DCACHE line bytes (and flags) on the Cortex-A9 core by reading/writing CP14 or (less likely CP15)?

    Lukasz
    Lukasz

    I'm trying to fix problems related to Dcache enabling on Cortex-A9 based board.

    Is it possible to inspect cache line data? How I should do it? Shall I use CP14?

    I do know that with Lauterbach's TRACE32 it was possible to modify and inspect cache content…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 single core

    Vincent Siles
    Vincent Siles

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

    Abhilash VR
    Abhilash VR

    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.

    From JTAG, Read works properly but writes makes the specific cache line corrupted,

    Step 1 : Initial Setup

         1. Wrote an application Which runs from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Differences between Privilege Modes and Non-Privilege Mode ?

    Rui
    Rui

    Hi everyone ,

    I'm currently using a Cortex-A9 processor (NXP Freescale i.MX6S).

    My project is to develop a simple OS, but I met a problem:   

    When I am trying to control some peripherals (such as UART and GPIO) directly under ARM USER MODE, the program…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 second execution unit

    Kushal
    Kushal

    Dear All,

    I am trying to understand the full working of execution stage in ARM cortex A9 and the types of instructions that are executed in second execution unit(ALU).

    Till now i was able to find quite limited references that were not much helpful.

    If any…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Need to invalidate L1 cache after DMA on Cortex A9

    Rohan
    Rohan

    Hi,

    I'm using a Renesas RZ/A1L, Cortex A9 microcontroller. After a DMA operation which transfers some data from a SPI module into RAM, I can't read the data correctly unless I've disabled L1 cache. (The base code which Renesas supplies sets the caches…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can we use PMU(Performance Measuring Unit) on Cortex A8 for calculating cycles on Simulator without hardware?

    Sridhar Artham
    Sridhar Artham

    ARMv7A family members will have PMU on the processor. Using this PMU, we can access cycle counts. Can we relay on this using the simulator?

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • wrong reset value of TTBR0 at reset, in Cortex A9, R3P0

    anoop
    anoop

    Hi

    i have some questions on dual Core CortexA9 r3p0 revision.

    I am using Cortex A9 r3p0 processor in Our SOC(system on Chip). when i connect to Core 0 and read TTBR0 register i get 0x00004001, but when i connect to Core1 and do read the same TTBR0 register…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • what are the main differences between cortex A7, A9, A53

    aaa
    aaa

    What are the main/important features added/updated?

    Thank you.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A9-PL310 AXI connection

    Luke
    Luke

    Hi experts,

    I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

    I think Figure 1.2 in the TRM is a good starting point:

    CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to handle SCU at runtime on Cortex-A9

    John
    John

    Hi there,

    I'm working on altera cyclone V SoC equipped with a Dual Core Cortex-A9. It runs Linux socfpga 3.13. I'm trying to disable (and enable) the SCU at runtime, but I have a segmantation fault: unable to handle kernel paging requet at virtual address…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • unaligned data fetch in Cortexa9

    anoop
    anoop

    I have a question related to data fetch, when on gdb debugger I do an address read say as:

    X 0x81000000

    Then it will fetch 64 bits as you told in reference to Cortex A9

    If further I do

    X 0x81000004

    Will it fetch 64 bits  again from 0x81000000 or it will use…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 flush cache

    Tamilselvan Shanmugam
    Tamilselvan Shanmugam

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use DMA for Cortex-A9 ?

    lijiao
    lijiao

      hello, I want to use DMA 330 asm code, but i can't compile it. can anyone tell how to use the PLL330 DMA assembly code? or tell me how to use the DMA for Cortex-A9

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 boot from spi-flash 32M

    Daniel
    Daniel

    Hi, we are using arm cortex-a9 booting from spansion s25fl256. We are confused why the spi driver forces to limits flash size to 0x1000000 (16M). It's normal when first bring up and into linux. However, we find the uboot is broken or overrided and can…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use the performance monitor of Cortex-A9?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,
    I feel I am an amateur.
    I tried to work the performance monitor of Cortex-A9 but it did not work.
    The followings are my codes.
    Please tell me what was wrong.

            mov     r3, #0
            mcr     15, 0, r3, cr9, cr12, {0} // PMCR PMU disable…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Context ID Register & Process Context Switch

    onion
    onion

    Hi, all

    What is the content of Context ID Register of ARM Cortex A9. Is it OS that is responsible for assigning the value

    of Process ID and ASID? As far as I know, it is so in Linux. Is that the same in the other OSes?

    Is it essential to deal with ASID if…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Software Radio Based on ZedBoard and AD-FMCOMMS1-EBZ

    hgli
    hgli

    ARM friends,

    I have done some research on software radio based on ZedBoard and AD-FMCOMMS1-EBZ.

    ZedBoard is a development board which uses Xilinx Soc FPGA.

    Xilinx Soc FPGA includes ARM Cortex A9 dual-core and Xilinx FPGA.

    ZedBoard runs Ubuntu Linux operating…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • question about arm cortex-a9 neon optimization(4x4 matrix mul)

    Jin, Soonjong
    Jin, Soonjong

    =======================================

    for matrix 4 by 4 multiplication, neon programming is slower than natural code with

    auto-vectorization option. (Xilinx Zynq 702 EVM board - cortex a9 with gcc complier option

    -mfloat-abi=softfp -mfpu=neon-fp16 -ftree…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
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