• Basic cortex A9 architecture question (memory area division)

    Senthil Kumar Rajagopal
    Senthil Kumar Rajagopal

    Hello all,

    I have a client who has the following requirement. He uses an Cortex A9 (dual core) based SoC chip .

    The system has two Flash ROMs - Flash ROM 0 and Flash ROM 1. Each of these flash roms has a boot loader and user program.

    On Reset, the CPU 0…

    • Answered
    • over 5 years ago
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  • D-side prefetch Cortex-A8

    Andreas Hauser
    Andreas Hauser

    Hi at all!

    At the moment I implement the initial routines and cache-handling for Cortex-A8. All the implementation is according the Boot-Code example in Cortex-A8 Programmers Guide on page 13-4.

    Now I'm a little bit confused about the handling for enabling…

    • Answered
    • over 5 years ago
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  • Supported AXI transfers on Cortex-A9?

    Martin Trummer
    Martin Trummer

    Hi folks,

    The technical reference states that only a subset of possible AXI transactions are actually generated.

    This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

    What happens for this table if the master…

    • Answered
    • over 5 years ago
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  • General Feature of Cortex processors on cache coherency

    techguyz
    techguyz

    Hi Experts,

    Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

    I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • The merit of data cache cleaning

    Henry Choi
    Henry Choi

    Hello everyone, my 1st question to the ARM community; please excuse my ignorance.  Fairly recently, I shared OCM (on-chip-memory) on Xilinx Zynq processor (which is dual ARM Cortex A9).  To pass message between the 2 cores, I followed the Xilinx example…

    • Answered
    • over 5 years ago
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  • How to run an ARM 32bit binary on Juno Board in Linux and Android ?

    zzliu
    zzliu

    hi, guys:

    Currently, i want to execute a Cotex-A9 binary compiled by ARMCC on Juno board(OS is linux).

    But when i ran it, it reported that "XX: No such file or directory".

    My questions are:

    (1) Did somebody meet this problem before ?

          and could…

    • Answered
    • over 5 years ago
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    • Cortex-A / A-Profile forum
  • Cortex-A9/GIC: de-activate an active interrupt

    42Bastian
    42Bastian

    Hi

    my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.

    No the problem: If the normal-world error happens in an…

    • Answered
    • over 5 years ago
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  • Cortex-A53 - GICv4 Documentation

    anoop
    anoop

    i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2

    • Answered
    • over 5 years ago
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  • Questions about Generic Timer in ARMv8

    wangchj
    wangchj

    When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

    But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

    And, if…

    • Answered
    • over 5 years ago
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  • How should I do if I want to enable only one single CPU on a Cortex A9 MPCore(2 CPUs)

    onion
    onion

    Hi, all

    When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged

    at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user

    space process VM (for Virtual Memory…

    • Answered
    • over 5 years ago
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  • How can we boot linux kernel in ARM FVP w/ TrustZone?

    Yoshiharu Imamoto
    Yoshiharu Imamoto

    Hello, everyone.

    Let me post a question regarding booting Linux on ARM FVP (with Cortex-A9 MPCore).

    I'm setting up an experiment which uses TrustZone on ARM FVP. I'm not sure which

    kernel to run in the secure world, but am sure to run Linux in Normal…

    • Answered
    • over 5 years ago
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  • STRD ATOMIC?

    loquat
    loquat

    Hi, I make a software for Cortex-A9 and Cortex-M4 (both uni-processor system).

    Question.

    Is 64bit-aligned STRD(64bit memory access) atomic ?

    (I know tha It is not atomic, but i don't know behavior.)

    For example:

    LDR R2,=buff

    mov R0, #1

    mov R1, #2

    STRD R0…

    • Answered
    • over 5 years ago
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  • Cortex-A9 PMU cycle counter not always incrementing at CPU frequency?

    Christian Ascheberg
    Christian Ascheberg

    Hello,

    I want to benchmark my program running on Linux on an Altera Cyclone V SoC board, but it turns out that the values returned from the ARM Cortex-A9 PMU cycle counter suggest that some sort of CPU frequency scaling is active, which is confusing me…

    • Answered
    • over 5 years ago
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  • cross compiling the hello trust zone example

    Sean
    Sean

    Is it possible for me to cross compile the hello Trust Zone example referenced here: Cortex-A9 TrustZone example ? The build file contains the command options for the arm compiler. I do not have the board this example was meant for, and I am trying to…

    • Answered
    • over 5 years ago
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  • Feature wise comparision for Cortex A series processors

    techguyz
    techguyz

    Hi Experts,

    Is there any document on feature wise comparison chart on the Cortex A series of processors ?

    Like,

    Cache for Cortex A8/9/52...

    MMU for cortex A8/9/52..

    • Answered
    • over 5 years ago
    • Processors
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  • Cache maintanance operation to PoC

    Luke
    Luke

    Hi experts,

    I'm quite confused about cache maintanance operation to PoC on Cortex-A9 (with PL310 L2 cache controller).

    I'm refererring to the following operations:

    - DCIMVAC, invalidate data cache by MVA to POC      (mcr  p15, 0, r0, c7, c6, 1)…

    • Answered
    • over 5 years ago
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  • Issue with WatchDog reset De-asserting

    BAB
    BAB

    Hi,

    I am working on ARM CortexA9 processor. I could able to enable both l4wd0 and l4wd1 watchdogs. Issue is system is resetting but not rerunning. I tried changing the register values of reset Manger as well.

    How to de-assert the reset and make the system…

    • over 1 year ago
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  • Watchdog timer not entering ISR

    sherry
    sherry

    I am using ARM cortex A9 core in Zynq. I want to trap any bugs in hardware or my firmware. I intend to use watchdog module in interrupt mode and connect it to Global interrupt controller (ScuGic). When the watchdog counter decrements to zero, it is to…

    • Answered
    • over 1 year ago
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  • Cortex-A9 TLB lockdown

    scribnote5
    scribnote5
    Hello, expert.

    I tried to implement TLB lockdown in Cortex-A9.

    Cortex-A8 and ARM1136JF RFP offer detailed TLB lockdown method but cortex-A9 RFP doesn't offer it.


    I tried TLB lockdown following Cortex-A8 and ARM1136JF RFP.
    0. Invalidate TLB with ASID…
    • Answered
    • over 1 year ago
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  • Count Main TLB miss

    scribnote5
    scribnote5

    Hello, experts:

    My platform is a Cortex-A9 MPCore CPU, Sabre Lite(i.mx6).

    I tried to count TLB miss so I implemented PMUEVENT to check micro TLB miss.

    But PMUEVENT doesn't support the main TLB miss event.

    In cortex-a9 RFP, "If there is a miss in main…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • A question aboout Monitor Vector Base Address Register(MVBAR)

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore CPU, It supports the trustzone tech.

    I tried to switch the non-secure world to secure world in Linux but It is hard to implement.

    I have a question about the trustzone about Monitor Vector Base Address…

    • Answered
    • over 1 year ago
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  • Flushing all L1 & L2 caches under Linux (kernel space) - optimizing dma-mapping API

    eli.z
    eli.z

    Hi,

    In my system (CycloneV - 2 cores of Cortex-A9) I require large DMA transfers, and currently I can't connect DMA via ACP, so cache coherency becomes SW problem. I know that the proper way of doing it under Linux is using the DMA-MAPPING API, and…

    • Answered
    • over 1 year ago
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    • Cortex-A / A-Profile forum
  • Why NSCAR(Non-secure Access Control Register) changes often?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore CPU, It supports trustzone tech.

    I tried to change NSACR.TL bit, but It needs to change in the secure state.

    I checked NSACR value in non-secure state and NSACR value that I changed is changed aperiodically…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use Secure Monitor Call(SMC) and entrance Monitor Mode?

    scribnote5
    scribnote5

    Hello, experts:

    My platform has a Cortex-A9 MPCore cpu, It supports trustzone tech.

    I want to change NSACR.TL bit, but It need in secure state.

    I want to change non-secure state to secure state by entering monitor mode using smc.

    But It is not easy to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • dump MMU translation table for A9 in Linux

    mivascu
    mivascu

    Hello,

         I would like to know how to read the translation table info for A9  from embedded Linux.

         In freeRTOS I have translation_table.S but I do not find anything similar for ARM architecure in linux kernel.

         Should I just dump TTBR0/TTBR1 registers…

    • Answered
    • over 1 year ago
    • Processors
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