For example, in ARM's related docments says that cortex-A7 support max to 4 cores and cortex-A8 support only one core, and the same time cortex-A7's pipeline is not the same with cortex-A8's pipeline. I want ask the cortex-A7's pipeline is for all the…

I'm seeing Cortex-A7 cycle-timing table here :

http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/

For example, 

VADD.F32 Dd, Dn, Dm takes 2 cycles

VADD.F32 Qd, Qn, Qm takes 4 cycles

same goes for VMUL..

Is this really the case…

On ARMv7 Cortex-A8/9/7, to map 4GB memory space, the minimum MMU table size is 16 KB(section mapping). Any possible to map 4 GB memory space with 16 KB MMU table, on ARMv8, AArch64 mode?