Hi everybody!!

I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).

In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…

Hello,

i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

Thank you.

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

Where can I find the docments about how the ARM cortex-A series pipeline works?

Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

What's the cortex-A7 pipeline's in-order and cortex-A15 pipeline's out-of-order mean?

In ARM's white paper(about the cortex-A7 and cortex-A15) says as follow:

I want ask the in-order and out-of-order mean what?

Cortex-A7 pipeline is non-symmetric, what does this attribute mean?

My understand is that cortex-A7 pipeline's five entries does not have the same two, in the contrary, the cortex-A15 have the two entries are the same.

Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.

According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..

How arm processor…

Hello,

I did experiments with Odroid XU3. I have noticed interesting effect of square root calculation.

I have received unexpected results, during experiments with execution time of 50 million square root operations.

  double temp = 5.0;

  double…