Hi all,

I'm trying to boot Linux on my hypervisor like environment.

In booting process, unexpected hyper trap was occurred and became hyp mode.

In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.

According to the manual, this meant "Fault…

What are the main/important features added/updated?

Thank you.

I'm trying to understand read allocate mode in cortex A7 core. From description of Read allocate mode in TRM of Cortex A7 core, my understanding is that bzero will downgrade memset performance while memset was done with consecutive memory.  For example…

Hi, I am using imx6ul board which has cortex a7 processor. I am using ffmpeg .s files which has assembly code to integrate into our project to speed up the code.  Here is the ffmpeg code in the file mdct_neon.S.

#include "asm.S"
.fpu neo…

Hi,

i'm currently trying to measure cycle counts for FIR-filtering with the NE10 library. I'm using a Raspberry Pi 2 with ARM Cortex-A7 running on Raspbian as a target.

I activated the Cortex-A7 performance counter register to read out the cycles…

I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

The CPU boots from an external 4MBytes SPI NOR FLASH chip.

It has 512 KBytes of L2 cache and 32 KBytes…

Hi experts!

As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
But barriers are even used in in-order cpus.
What is for?
Can…

Hi all,

I am working on OrangePi board. The board configuration is,

• Quad-Core ARM Cortex-A7, 1.6 GHz
• 32 KB L1 I-Cache and 32 KB L1 D-Cache per core
• 512 KB L2-Cache

I have few queries related to Cache memory,

1. How to disable L2 cache of Cortex-A7 in…

I am trying to run two Cortex-A7s in AMP configuration with Linux running on one core (SMP disabled) and baremetal/RTOS running on other core. I am having difficulty in setting up SGIs (IPIs) between the two cores. I am at a point where both of the cores…

Hello,

i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?

Thank you.

Hi,

I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

we can see several information regarding a cache line. Those are:

1. Current data in cache

2. its 4-bit MOESI state,

3. Outer Memory Attribute

4. its tag

5. NS State.

However…

Hi all,

I am trying to connect to the RPi2 JTAG.

I have the following setup

- Raspberry Pi 2 running Raspbian 8.0 (Jessie)

- OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.

I setup the GPIO in order to expose the JTAG interface and the…

Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!

hi, experts:

I found ACTLR register definition is different between Cortex-A7 and Cortex-A9.

I have some questions about out cache concept in Cortex-A7.
1. Some program disable outer cache by setting ACTLR[1] = 0.

   So, is it only available with Cortex-A9…

Hi,

I just got a raspberry pi 2 and I'd like to play with Trustzone.

People on the Raspberry forum http://www.raspberrypi.org/forums/viewtopic.php?p=697474#p697474 explained me how to

get my hand on the boot of the 4 core A7 CPU, and I managed to boot…

Hello,

I have an IP with an ACE-Lite I/F which can issue a 128Byte write transaction with a "WriteLineUnique" type. I  the system there will be a cortex A7 master(64bytes cache line). My question is: in case of such transaction (WriteLineUnique with 128bytes…

What can be accessed by MRS/MSR in user mode?

In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):

I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found

an answer to in ARMv7-A/R ARM Issue C.

How is this special?

When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.

But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......

And, if…

If a region is marked as non-cacheable, will the CPU also first check the cache when CPU want to access the region?

In cortex-A7 spec, it says" the core hardware will check all instruction fetches and data reads or writes in the cache, although obviously…

Where can I find the cortex-A7 related 8 stages pipeline docments?

I have found some docments about this but all are too brief, so I want ask where can I find the detailed docments?

In cortex-A7 it has 8 stages pipeline, so PC's value is current program address add how many bytes?

Where can I find the docments about how the ARM cortex-A series pipeline works?

Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…

Cortex-A7 structure can support max to 4 cores, I want ask the 4 cores have 4 part copy of the registers(37 registers * 4)?

In other words, each core have the same 37 registers or the 4 cores share the 37 registers?