What can be accessed by MRS/MSR in user mode?
In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):
| B9.3.10 | MSR (Banked register) |
| cond | 0 0 0 1 0 R 0 0 | M1 … |
MRS/MSR (Banked register)
- over 5 years ago
- Processors
- Cortex-A / A-Profile forum
Still more stupid questions on Cortex-A7 instruction set
I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found
an answer to in ARMv7-A/R ARM Issue C.
How is this special?
| LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case… |
- over 5 years ago
- Processors
- Cortex-A / A-Profile forum