Hi everybody!!
I have a question on how get cache size on ARM v7-A, more specifically on A9 (or A7 or A15).
In accordance with the TRM at page 1529 I get the value from CSSIDR register and I compute the cache size. More precisely, I do cache size = num…
Hi all,
I'm trying to boot Linux on my hypervisor like environment.
In booting process, unexpected hyper trap was occurred and became hyp mode.
In hyp mode, the Hyp Syndrome Register (HSR) value is 0x93830006.
According to the manual, this meant "Fault…
What can be accessed by MRS/MSR in user mode?
In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):
| B9.3.10 | MSR (Banked register) |
| cond | 0 0 0 1 0 R 0 0 | M1 … |
I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found
an answer to in ARMv7-A/R ARM Issue C.
How is this special?
| LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case… |
When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.
But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......
And, if…
Is there a reason why banked registers SP and LR can't be accessed as r13_<mode> or r14_<mode>, but
one has to use SP_<mode> or LR_<mode> instead? It makes macros and inline assembly difficult.
In document (ARMv7-A/R ARM Issue…
I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…
Hi !
Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).
We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…
Hello Guys,
Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.
Here is the list of measurements which i want to perform.
1) FIQ latency when RTOS runs and FIQ occurs …
I use a Cortex-A7 board and write start up code.
I try to use Security Extension.
I use `smc` instruction and make cpu mode monitor mode.
In the monitor handler, I tried to changed stack pointer value for calling other functions.
But after execute `ldr sp…
