Hi ,
I am running aarch32 app in ARMv8a( cortex-a57 ) device. The performance reports ( using gettimeofday() utility ), showing large spikes on random calls. But the same app on ARMv7a( cortex-a15 ) device is quite stable.
Will the aarch32 library…
Hi ,
I am running aarch32 app in ARMv8a( cortex-a57 ) device. The performance reports ( using gettimeofday() utility ), showing large spikes on random calls. But the same app on ARMv7a( cortex-a15 ) device is quite stable.
Will the aarch32 library…
I asked this question in a different community space but it seemed like this is a more appropriate home.
I'm trying to configure the performance counters for the Cortex-A57 and I'm very confused. The technical reference manual alludes to accesses being…
The TRM for the a-57 states that PMCEID0_EL0: Defines which common architectural and common micro-architectural feature events are implemented. PMCEID1_EL0 is a continuation of this list. If a bit position is a "1" that means the even is implemented…
The technical reference manual states that the Cortex-A57 generic timer events are not affected by CPU clock frequency change. My challenge is that I can't use any built in linux libraries to create a delay because whenever I try it clears performance…
Hello,
I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?
Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…
Hi,
I start to learn and program TZC-400 in FVP Cortext57-A Base platform with DS-5, and encounter something that I don't understand.
I start the FVP as non-secure mode by using the paramter "bp.secure_memory = false". Then I poll TZC's gate_keeper…
I'm getting a SIGILL when running a ARMv6 program in a chroot environment.
The instruction that triggers it is
Program received signal SIGILL, Illegal instruction. 0x000104f0 in f () (gdb) disassemble $pc Dump of assembler code for function f: => 0x000104f0…
hi :
I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).
however, I can not find any clue about flushing L2 cache to DRAM(if without L3).
and I saw some points that L2 flushing was not needed.
for ARMv8, how can…
Two questions:
1. Where can I find the detailed explanation of ARM PMU events?
2. How to know the stall cycles for e.g. icache miss etc.?
Thanks.
Hi Experts,
Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?
Hi experts,
I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER?
Thanks.
Hi Experts,
Is there any sample development boards available on Cortex-A72/5x series ?
Regards,
Techguyz
Hi, can anyone suggest me how to know the instructions cycle timing of the arm_v8 instructions.does it take more cycles to transmit from neon to basic arm instructions in arm_v8.
please suggest me how to calculate instruction cycles in arm_v8
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…
First sorry my english writing level. :-)
In non-secure world using android system(linux kernel).
I use big.little core Cortex-A53, Cortex-A57
I was tested to 2case.
previous stage.
1. Linux allocation memory using(malloc or mmap)
Hi Experts,
I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.
While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.
When I run world shared memory test on a single core (using affinity), it works…
Hi ARM experts,
For shareability attribute, have some confusions:
1 For a memory location with cacheability attribute, does hardware do "flush" action after "writing" to push data to end if shareability attribute is also set. Otherwise…
Hi,
I heard that some 10-Gb Ethenet chip embedded an ARM core. I am curious about what type of ARM (A, M or R) is embedded in such a high speed Ethernet ASIC. I feel that it may be a R series ARM. Is it right? Due to such a high speed data rate, what chip…
Hi Experts,
Does the Reset Management Register will be implemented mandatory or optional for the SoC based on ARMv8 and how it is practically used ?
Regards,
Techguyz
Hi Experts,
What are all the list of integrated debug functionalities in ARM v8 which will be affected by the cold and warm resets.
Regards,
Techguyz
I am looking to emulate an Apple II and would like to specify some address ranges as being memory mapped so that any access would result in perhaps an interrupt that I am then able to handle and in which I can determine the memory address being accessed…
I'm looking to emulate a 6502 on the ARM but I would like to make it cycle accurate so I need some way to interface to an external clock. I can't rely on an internal clock as there are external components that will rely on the external clock as well and…
Hi,
I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.
The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.
There is no L3 cache. So the memory…
Hi experts,
I am recently developing some bare-metal code for a Cortex-A57 Aarch64 on QEMU (Virt platform) for playing with the Virtualization Extension. I first used one core and I developed a bootloader from scratch that switches the execution from…
Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57.
Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension
Let assume a physical interrupts acknowledged by hypervisor in…