Hi experts,
I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?
Is it possiable if we make more cores per cluster? if not, what is the limitation?
Does CCI-400 guarantees cache coherency between secure and non-secure worlds?
Hi Experts,
I'm developing some kind of Secure OS on A57/53 big.LITTLE SoC.
While multi-core testing, I'm facing some wired problem on my world shared memory mechanism.
When I run world shared memory test on a single core (using affinity), it works…
- over 5 years ago
- Processors
- Cortex-A / A-Profile forum
shareable domain and cache policy problem
Hi,
I'm trying to find out what level is the out-most level of inner shareable domain. Is there any register to get this information? I want to know what inner shareable domain is in A53 big-LITTLE architecture. I find some articles that telling L1 and…
- over 1 year ago
- Processors
- Cortex-A / A-Profile forum