What are the main/important features added/updated?

Thank you.

Which arm processor has the largest number or cores?

Could anyone give me the code to get the current secure state?

Hi experts!

As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
But barriers are even used in in-order cpus.
What is for?
Can…

The working secerio is that I'm testing OP-TEE on a Hikey board(Cortex-A53, armv8), and they use arm-trusted-firmware(see https://github.com/linaro-swg/arm-trusted-firmware) to be the monitor running in EL3.

I'm trying to access some resources in EL1…

Hello?

This is SoYeon Kang.

I'm Korean.

I want to purchase

Cortex-A53.

How can I buy it???

Then, I want to ask

for the cost of Cortex-A53.

What's the one product cost?

Then, how much several product costs?

Hello,

I am looking for a development board that has an open Trustzone and hardware virtualization support. Do the Juno boards support this?

Looking around the ARM A72/57/53 chips all support Arm Trustzone and have hardware virtualization support, however…

Hello,

I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

hey,

How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

can anybody tell me…

The TRM for the Cortex-A53 has a section on direct access to various internal memories, including the L1 I-cache and D-caches. I'm successfully able to dump both tag and data for the I-cache and D-cache, but I'm having trouble making sense of the I-cache…

Need specific references to the hardware interrupt latency for the ARMv8 Cortex-A53.  interrupt latency from when an interrupt is triggered to when the ISR is initially invoked, but not including operating system, kernel, or application latency.

Hi,

I am experimenting execution level switching on A53. I go from EL3->El2, then call SMC instruction to return to EL3. As soon as SMC instruction is executed, the processor enters EL3 mode and an exception is generated.

I have written an exception…

Hi,

I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

we can see several information regarding a cache line. Those are:

1. Current data in cache

2. its 4-bit MOESI state,

3. Outer Memory Attribute

4. its tag

5. NS State.

However…

Hi experts,

I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

Is it possiable if we make more cores per cluster? if not, what is the limitation?

Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!

I find the description below from MMU-500 TRM.

Address width

The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

bus…

Where can i get a list of all these family of ARM processors and their differences

hi,

     I'm studying Cortex-A53 cache process. I run the following cache invalid program, but the result is cache not invalid.

     Could you give me any suggestion about cache invalid? Thanks!

     The program…

Dear ARM Group,

Can we run the A53 cores at different clock speeds?

if YES,  How does it effect the complete A53 (L2 cache etc) and system?

if NO,  What are the constraints ?

could you please give a detailed description on this?

Thanks,

Ravinder…

Hi Experts,

Whether the ARM provides the power management controller inbuilt in the cortex A5x processors or it provides signal pins suitable for easy integration with the power management controllers ?

I'm testing GIC and ARM A53 connectivity. I can see that GIC is forwarding the IRQ request and ARM core has received it(shows in ISR reg). However, my IRQ handler is not getting called. Here is how I'm registering it..

void main () { 
... 
__enable_irq…

Hello all,

I have a A53 based platform. There are multiple IRQ sources, some of which fire at the same time. To avoid recursive IRQ handler calls, I have disabled IRQs' on entry in IRQ handler and enabled them befor exit. However, at one point, there is…

For example, one M4 is a client of SMMU, and its MPU had been configured to map some memory(MEM_A) as inner outter write-back, how the configureation of SMMU context transcation table will affect the access attribute, say, the transcation table mark …

Hi experts,

I want to know if there are CPUIDs information in CHI interface about IP A53/57 Mpcore? and can CCN504 transfer the CPUIDs to Slave device? for example, AXI_USER？

Thanks.

Hi Experts,

Is there any sample development boards available on Cortex-A72/5x series ?

Regards,

Techguyz