• Data Abort Exception in A53

    Geeta Phuloria
    Geeta Phuloria

    Hello,

    I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    zynq
    zynq

    hey,

    How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

    in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

    but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

    can anybody tell me…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
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