hi.

I have a question about floating point performance relative with fpsr register.

When i initialize hardware, there is floating point exception(inexactly floating-point exception).

I did not set fpcr.IXE=0, so fpsr.IXC is set. not occur exception.

I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

I tried -mfpu…

I am using ARMv8 GCC compiler and I would like to optimize Neon Intrinsics code for better execution time performance. I have already tried loop unrolling and I am using look up table for the computation of log10. Any ideas?

Here is the code:

static inline…

I am failing at searches can someone point me to a reference for the banked registers for an FIQ in AARCH64 on a cortexA53

I can find hundreds of references for AARCH32 banked registers but none for AARCH64

I have largely ignored the FIQ to date just…

Hi,

I am reading the A53 MP Core doc.

My question is related to instruction preloading in aarch64.

In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

Question 1:  Will the PLI instruction first…

Hi,

Im new to ARM. Im learning generic timers in cortex a-53. I wanted to know whats the meaning of "system level implementation" of Generic Timer and "PE implementations" of the Generic Timer.  How is it different from Generic timer…

Please clarify that with me... With

"The current Program Counter (PC) cannot be referred to by number as if part of
the general register file and therefore cannot be used as the source or destination
of arithmetic instructions, or as the base, index…

Hi all,

I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

/tmp/cc7Dc236.s: Assembler messages:
/tmp/cc7Dc236.s:31…

I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

Hello experts,
I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

Hello everyone,

I'm trying to wrap my head around the MMU configuration for Cortex A53 armv8 architecture (AArch64). Specifically, I'm programming for Raspberry Pi 3 (Bare Metal).

I've successfully setup the page tables for two levels covering…

Hello everyone,

I'm experimenting a bit with MMU after understanding its core principles. Specifically I can successfully enable it with an identity mapping for TTBR0 (no TTBR1) on a Raspberry Pi 3 (Cortex A-53, ARMv8 AArch64).

The next step I wanted…

I have been trying to do a preemptive context switch on interrupt on the Cortexa53 but it isn't working can anyone spot an error in the code.

The code has no FPU use so it is supposed to be just a lazy save and restore registers.

The restore section…

Hi,

Iam wondering if it makes sense to have a memory barrier after access to a memory mapped register. I looking at a driver, unfortunately not open source, that has a memory barrier after a read from the interrupt status register of the peripheral when…

Since ARM caches are physically indexed is there any way to flush based on the PA? I know I can get the set, but what about the way? If I am flushing from L1 would I have to flush all ways in L1 and then L2 assuming there is no L3 to get to system memory…

Hi,

I have done some basic assembly in Armv7-A processors (cortex A9). The version of ARM supports modes like User, sys, SVC etc. Does the ARMv8 also has the similar modes? Where can i find the details. Please point me to the documents if any.

Regards…