Hi,
I have strange symptom with Cortex-A15 device.
The below is traced data.
Program AddressDisassembly
0x40401AA0CMP R12, R0
0x40401AA4BHI 0x40401A80…
Hi,
I have strange symptom with Cortex-A15 device.
The below is traced data.
Program AddressDisassembly
0x40401AA0CMP R12, R0
0x40401AA4BHI 0x40401A80…
Hi experts! I have a question about cache instruction.
DDI0406C_b_arm_architecture_reference_manual for Armv7 says
Effect of the Multiprocessing Extensions on All and set/way maintenance operations
The only architectural guarantee for the following…
I am looking for a appropriate CortexA15 development board. If the price is less than $1000, or even $500, so much the better
Does anyone have the suggestion with such board?
Thank you!
Hello community and experts,
I am having a troubled time to understand the memory barriers. The further I read, the further I am being paranoid about the speculative reads and cpu re-ordering.
I will have some questions and I will really appreciate any…
For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.
How can we measure the CPU utilization of programs running on ARM processors, particularly the A15 series ? Are there some hardware counters that can be read ?
Hello,
i was wondering if the voltage levels for dvfs states are fixed at the design time. For example for Cortex A7 or A15. Is this information available?
Thank you.
Dear,
I am an greenhand developer on cortex-a15.
now I need some specification as follows:
where I can get the instruction set of cortex-A15?
are there some documents about optimization technology on cortex-A15(image processing optimization)
Thanks a lot.
Respected Experts,
I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on …
All,
When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:
asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));
sleep…I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…
i just want to know which processors are very advanced processors in cortex-A,R and M series.
When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.
But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......
And, if…
Where can I find the docments about how the ARM cortex-A series pipeline works?
Such as the first step of the pipeline do what and the second step of the pipeline do what, and also the Cortex-A series has different pipelines(such as cortex-A7 is different…
Hi all,
Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.
U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too…
Dear All,
Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it?
Thank you so much.
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…
Hi, all
When I was porting Minix 3 OS to Zedboard (Zynq 7000 All Programmable SoC) the system always hanged
at refresh_tlb. What's strange is that refresh_tlb had been performed at KERNEL booting up, but when a user
space process VM (for Virtual Memory…
Hi forks. I am a newbie engineer for arm-processor and I have a question about VMSAv7-32.
According to ARMv8 architecture manual, page 3592: arm processor can skip first level table if a first level table would contain only one entry..
How arm processor…
Hi, experts.
I'm developing pagetable on exynos5250 and exynos5433.
But i have very strange problem....
when i mapping secure-memory-area as section with attributes that is
S = 1, TEX= 001, C =1, B = 1 => Outer and Inner Write-Back…
What's the difference between core, processor,cluster and CPU?
Hi,
When I read Thumb-2 instruction manual, it is not clear to me about SDIV availability. Especially I do not understand the last line "are not available in ARM state."
Could you explain it to me?
Thanks,
New functionality introduced with Thumb…
Hi,
I heard that some 10-Gb Ethenet chip embedded an ARM core. I am curious about what type of ARM (A, M or R) is embedded in such a high speed Ethernet ASIC. I feel that it may be a R series ARM. Is it right? Due to such a high speed data rate, what chip…