• Different performance in HYP and SVC mode ARMv7A?

    ivanpavic
    ivanpavic

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • To run library functions on arm a53 core

    Sagar K
    Sagar K

    Hello experts,
    I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A15 SCU

    Yang Wang
    Yang Wang

    Hi,

    I find no introduction about SCU registers of A15 in the TRM.

    So, can software control SCU? Especially is SCU needed to be enabled by software?

    Thanks&Regards.

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to flush the pipeline of a processor using XScale-compatible Assembly?

    rbedin
    rbedin

    Hello,

    Some friends and I are playing with a Cortex-A15 core (using a Beagleboard) but, due to compatibility with some legacy code, we need to use the --cpu=xscale option when building our executable. We were able to perform a board startup by using the…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Square root calculation results. FPU logic of A15 and A7 CPUs on Odroid-XU3 board.

    Rem
    Rem

    Hello,

    I did experiments with Odroid XU3. I have noticed interesting effect of square root calculation.

    I have received unexpected results, during experiments with execution time of 50 million square root operations.

      double temp = 5.0;
    
      double…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why does the ARM A15 processor have so many DVFS levels ?

    Kiran Chandramohan
    Kiran Chandramohan

    For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM SPEC score.

    Mazen Ezzeddine
    Mazen Ezzeddine

    Dear All,

    Does ARM  offer any official/reliable  SPEC2000/2006 benchmark results for  A15 cores? I am running some experiments and need to make comparisons.

    Thank you.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM cortex A15 hardware simulatenous multihreading.

    Mazen Ezzeddine
    Mazen Ezzeddine

    Dear All,

    Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it?

    Thank you so much.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to set secondary core's registers from primary arm?

    serhat
    serhat

    Hi all,

    Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.

    U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Measuring the time of a world switch

    Mazen Ezzeddine
    Mazen Ezzeddine

    Dear all,

    Consider a scenario where a bare minimum hardware-assisted hypervisor is hosting 2 simple guest OSes on a dual-core Cortex-A15. I want to accurately measure the time it takes to switch from the guest OS to the hypervisor and then from the hypervisor…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Difference between revisions

    Mohamed
    Mohamed

    Hello,

    I'm very new at the community, I want to start working with the ARM cortex A15, while looking for the datasheet, I got the page ARM Information Center, where I found a LOT of information about the processor,

    my question is about the different…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • behavior of executing instructions on the out-of-order pipeline of Cortex-A15

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I have one question regarding the interrupt of A15 core.

    Please see the below picture.

    Cortex-A15Pipeline.jpg

    I would like to know which area existing instructions are discarded when the interrupt happens. When an interrupt occurs, some instructions on Out-of-Order pipeline…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Interrupt on Out-of-Order pipeline of Cortex-A15

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I would like to know the interrupt behavior on Out-of-Order pipeline on Cortex-A15.

    When some instruction is executing on Out-of-Order pipeline, one interrupt is happens.

    In this case, its interrupt must wait until finish the current executing instruction…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Exception / Interrupt for Cortex-A15

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I would like to know whether my understanding is right or not regarding to the interrupt (exception).

    When an interrupt is issued, the interrupt is executed at once without the completeion of the executing instrructions.

    And, the contents of the result…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Out-of-Order of Cortex-A15 core and an interrupt

    Michihiro Yamamoto
    Michihiro Yamamoto

    I would like to know an behaviour of the interrupt on out-of-order.

    In-order situation :  The interrupt is issued at once because the instruction that is not completed is discarded.

    Out-of-Order situation : The interrupt is not issued until the instruction…

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A8/A15 L1 cache

    Michihiro Yamamoto
    Michihiro Yamamoto

    Hi,

    I would like to know whether the cortex-A8/A15 L1cache has ECC or parity check for error checking, or not.

    I know L2 cache has ECC function. Bur I don't know about L1 cache.

    Please let me know.

    Best regards,

    Michi

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • compiling kernel: -mcpu=cortex-a15 vs -march=armv7ve?

    Aid Farhan Maarof
    Aid Farhan Maarof

    I'm compiling an Android kernel for my Xperia Z using Linaro GCC 4.9. My question is, which option gives better optimization -mcpu=cortex-a15 or -march=armv7ve? Or do they give the same results?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Question regarding A15 L2ACTLR register programming (auto clock gating)

    Thomas P Abraham
    Thomas P Abraham

    Hi,

    This question is regarding Cortex-A15 L2ACTLR[27] bit ("Force L2 logic clock enable active"). If the clock to L2 block has to be forced to be active all the time (L2ACTLR[27] = 1), is it sufficient if one of the A15 Cores in the MPCore setting this…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to get fastmodel license for cortex-A15

    sweta
    sweta


    Hi,

    I have downloaded evaluation based fastmodel version 7.1 from arm fastmodel download link (https://silver.arm.com/browse/FM000).

    I want to load debugger model for cortex-A15x1 on fastmodel simulator but this shows me license error...

    ERROR: License check…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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