• Multi core L1 cache coherent

    Jorney
    Jorney

    Dear experts,

     I'm going to implement multi-core(4 cortex-a53) in my private OS. I have an issue which needs your confirmation.

    Q. When core0 invalidates the L1-cache and L2-cache at VADDR(Cached), Can other cores  get the right data at VADDR ?

    For…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • indirect branches in ARMv8

    MarekBykowski
    MarekBykowski

    Please clarify that with me... With

    "The current Program Counter (PC) cannot be referred to by number as if part of
    the general register file and therefore cannot be used as the source or destination
    of arithmetic instructions, or as the base, index…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 Generic Timer Clock and Operation

    Sajjad Ahmed
    Sajjad Ahmed

    Hi,

         I'm using NXP imx6ul-evk(single core cortex-a7 processor) and I'm trying to operate CPU at different frequencies(642MHz, 480MHz, 100MHz, 12MHz) and experiencing time drift on certain frequencies (Generic Timer's time lags Real Time), I'm using virtual…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Trustzone FIQ latency measurement When security extension is enabled

    Ashwin
    Ashwin

    Hello Guys,

    Please refer below attached image. as shown in this image i want to measure the different latencies in my Trustzone based application.

    Here is the list of measurements which i want to perform.   

    1) FIQ latency when RTOS runs and FIQ occurs …

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • GIC-400 controller virtual interrupt handling in VM and hypervisor

    Balraj Ramalingam
    Balraj Ramalingam

    Hi, I am new to ARM architecture and as of now exploring GIC Controller GIC-400 and using ARM Cortex a57.

    Sorry for asking very fundamental flow of interrupts handling GIC-Virtual extension

    Let assume a physical interrupts acknowledged by hypervisor in…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which register are dedicated for each MPCore in ARMv8-A architecture?

    StanleyDDD
    StanleyDDD
    Hi  Expert,
    I'm a beginner to ARMv8-A architecture MPcore and now studying A35 MPCore processor documents for low-level software developing.
    One question, when I read DDI0487C_a_armv8_arm and DEN0024A_v8_architecture_PG, from my understanding, there…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to access the system control register?

    aketh
    aketh

    Hi all,

    I am trying to access the system control register in my ARM C program. The code (with heading 64 bit) I used is presented below. However I got the following error message during compilation.

    /tmp/cc7Dc236.s: Assembler messages:
    /tmp/cc7Dc236.s:31…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Information about ARM System control registers.

    aketh
    aketh

    Hi all,

    I noticed there are multiple system control registers in ARM.

    The SCTLR_EL1 , SCTLR_EL2 and SCTLR_EL3.

    I want to know, what do multiple such system controls registers represent??

    I am particularly interested in the A bit of the system control register…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Feature Comparison ARM v8 series

    techguyz
    techguyz

    Hi Experts,

    Please specify is there any document on the Cortex A series comparison sheet for the various properties.

    For example, Table 2.1 in the https://static.docs.arm.com/den0024/a/DEN0024A_v8_architecture_PG.pdf has details on A53 and A57. Likewise…

    • over 2 years ago
    • Processors
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  • ARMv7-A: Cache maintenance operation by VA, performance

    Niklas
    Niklas

    Hi,

    according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • code is not working for optimization setting O2 and O3 for Arch64bit Cortex-A53 process

    Hemanth Kumar T
    Hemanth Kumar T

    I come across strange issue with Optimization setting O2 and O3 option my code will not work due to PC corruption, with O1 and O0 code woke fine, our target procesor is Arch64bit Cortex-A53. how to fix this issue. my i know what is the limitation of Heap…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Text section size for executable created with ARMCC 6.7 is more than expected

    Mubin
    Mubin

    Hi,

    I am porting Xilinx standalone drivers and libraries to armcc 6.7 compiler. I tried xilinx hello world application
    with the ported code base (for cortexa53 processor), and obseverd that text section size is ~82 KB. However, if i compile same hello…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • AM3352 core hang-up

    takashi
    takashi

    Hello,

    We are encountering the core hang-up of unknown origin in our mass-produced board using TI's AM3352 and Linux Kernel 3.13.4.
    Regarding the reproducibility of the test, some units had the hang-up to take about 2000 hours after a system start…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Quad-Core Cortex A7 / MSDOS comparability

    Scottie
    Scottie

    I just bought a Samsung SM-T560 (WiFi) SM-T561 (3G & WiFi) with a 1.3GHz: Quad-Core Cortex A7. I know nothing about processors but in searching the Internet I have found some applications that will allow Windows OS to run an Android system.

    Is the 

    …
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • To run library functions on arm a53 core

    Sagar K
    Sagar K

    Hello experts,
    I am working on a53 core in which I am not able to run string library functions like memset, memcpy etc. I have included the string.h library also but it is generation an exception. The same code works on the a15 core without any modification…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Ways to Tx data from Cortex R5 to A53?

    Zombie_Ashish
    Zombie_Ashish

    Hello,

    I'm trying understand the capabilities of both the cortex R5 and A53 but stuck at the point where i want to communicate to each core (A53 - Quad Cores and R5 - 2 Cores) in parallel. Can some one help me in understanding this or point to the related…

    • Answered
    • over 2 years ago
    • Processors
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  • ARM MUL instruction

    Juha Aaltonen
    Juha Aaltonen

    Still more instruction things giving me head ache.

    This time it's the MUL-instruction.

    What the heck means:

    Multiply multiplies two register values. The least significant 32 bits of the result are written to the destination

    register. These 32 bits do…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM PMU access DRAM Event

    pa007
    pa007

    Hi, accorting to the reference manual of cortex A7 https://static.docs.arm.com/ddi0464/f/DDI0464.pdf

    pagina 243, what event number i neet to select to count all the DRAM access (read / write)?

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Behavior for other data on a STR (ARMv7-A)

    superdesk
    superdesk

    When the following line is executed, what is the behavior with respect to the other words in the cache line?

    STR r1, [r0]

    The 4 bytes of data in r1 is written to the address in r0. But cache-lines are 32 bytes long. Assuming write-through (and ignoring…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can we reset L2 subsystem for cortex-A57?

    MarekBykowski
    MarekBykowski

    My system hosts 4x clusters, each with 4x cpus A57 connected through interconnect CCN504. I have a special case in which I need to reset L2 sybsystem (L2 is 2MB in my case) from inside SPL Uboot running from a static memory. The memory is attributed to…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • L2 TLB internal memory access through RAMINDEX

    Amitra29877
    Amitra29877

    Hi Experts,

    I need to access L2 TLB internal memory for A76 core (Section A6.6 of Cortex A76 TRM) . I was searching for an example code and found this for A57 core:

    LDR X0, =0x0000000001000D80
    SYS #0, c15, c4, #0, X0
    DSB SY
    ISB
    MRS X1, S3_0_c15_c0_0…
    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Can't find many microprocessor manufacturers with Cortex-A7 architecture?

    Omid
    Omid

    My understanding is that ARM Cortex-A7 architecture was released after Cortex-A9 and improves features of previous versions. However, I have only found one manufacturer, NXP, that uses Cortex-A7 architecture in their processors. I am referring to manufacturers…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Advantage of Zero register over the cost of implementing it ?

    Hpc_me
    Hpc_me

    Hi,

    I've heard that the cost of implementing a register is more.

    In ARMv8 there is a Zero register XZR/WZR, so what is the benefit of implementing such a register over the cost of implementing it?

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • GIC500 + CPU Interface - CA53

    Ryan100
    Ryan100

    Hi,

    I am triggering PPI or SGI interrupt on gic500 which will then communicate with CA53 over cpu interface and interrupt routine will be executed. 

    After interrupt routine is executed, we can write to cpu interface End Of Interrupt Register to "clear" interrupt…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What exactly is a full implementation of ARMv8.2-A?

    khunter
    khunter

    The technical spec for ARM Cortex A-75 claims that it supports a full implementation of ARMv8.2-A. The documents I have been able to reference only point to ARMv8A. Specifically I'm looking for what ARMv8.2-A brings to the SIMD table other than fp16 arithmetic…

    • Answered
    • over 2 years ago
    • Processors
    • Cortex-A / A-Profile forum
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