Hi Experts,
Is there any sample development boards available on Cortex-A72/5x series ?
Regards,
Techguyz
Hi Experts,
Is there any sample development boards available on Cortex-A72/5x series ?
Regards,
Techguyz
What can be accessed by MRS/MSR in user mode?
In ARMv7-A/R ARM there is an encoding for ARMv7VE (A1):
| B9.3.10 | MSR (Banked register) |
| cond | 0 0 0 1 0 R 0 0 | M1 … |
Hi
my situation: Running an OS in normal-world which due to an (user) error enters safe state with interrupts disabled. The Hypervisor enters by an FIQ (watchdog) and should reset the normal-world.
No the problem: If the normal-world error happens in an…
i am seeing an issue while doing Dhrystone test. i am using Dhrstone source code of version 2.1.
when i run this source code on LINUX platform, i got DMIPS/MHz =1.6
but there are some printing commands that prints variables used, when i disable them i got…
Does anyone have details of the current situation in this area? For example, has ARM recently announced any related product(s)? What products are available for the Cortex -A17, for example? In particular, what are the non-proprietary options, if any…
Hi
I have an inquiry. our company is using Cortex-A9 quad Core. So in ARM website there are many technical reference manuals for the same in different revisions , such as:
r2p0
r2p2
r3p0
r4p0
r4p1
so what should i follow?
or should i follow latest revision?
or…
Hi, can anyone suggest me how to know the instructions cycle timing of the arm_v8 instructions.does it take more cycles to transmit from neon to basic arm instructions in arm_v8.
please suggest me how to calculate instruction cycles in arm_v8
i have 1 more query related to GIC. in Cortex-A53 it is mentioned that it is using GIC 400 and GIC architecture Version 4, but in ARM site i am not seeing any GIC V4 Doc, there is only GIc v2
I wonder if the bit 22 has some function in instructions like LDRH, STRH, LDRSBT, LDRD, ... (bits 27, 26, 25 = 0, 0, 0)?
| 22… |
I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found
an answer to in ARMv7-A/R ARM Issue C.
How is this special?
| LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD<c>_<Rt>,_<Rt2>,_[PC,_#-0]_Special_case… |
In
ARM Cortex-A Series Programmer’s Guide for ARMv8-A: 13.2.4. Non-temporal load and store pair
it talks about a relaxation of the memory ordering requirements and then gives the example
LDR X0, [X3]…
Hi Experts,
As the general discussions seen in the community, it would be great if there is a general guidelines on the list of criteria or guidelines involved in the selection of Cortex A/R/M series Processors ?
Rather than application specific some other…
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for matrix 4 by 4 multiplication, neon programming is slower than natural code with
auto-vectorization option. (Xilinx Zynq 702 EVM board - cortex a9 with gcc complier option
-mfloat-abi=softfp -mfpu=neon-fp16 -ftree…
When two clusters(Big/Little) exist in SoC, the timer can be used to support Synchronization between two clusters.
But How to understand "Synchronization", anybody can tell me some typical application context? I am really confused......
And, if…
I am running on cortex-A17.
when following,
step1: STR R0, [R1] ; [R1] is cacheable
step2: DCCIMVAC ; clean and invalidate cache
step3: LDR R0, [R1] ; memory…
Hello all,
I was debugging an imprecise external abort in one of our product based on i.MX6q and came across a register - Auxiliary Data Fault Status Register
readable and writable by the following instructions -
MRC p15,0,<Rt>,c5,c1,0
MRC p15,0,<Rt…
Hi all,
Im working on Keystone II Tci6638k2k(4arm+8dsp) custom design board with u-boot. I understand that how u-boot working.
U-boot gives entry point to other cores. Other cores take program counters with this way. But i want to give core registers too…
Dear All,
Does ARM cortex A-15 support some kind of Hardware multithreading? how can I disable it?
Thank you so much.
Are there differences between coprocessor instructions and instruction2:s?
I mean:
MCRR vs. MCRR2
MRRC vs. MRRC2
MCR vs. MCR2
MRC vs. MRC2
LDC vs. LDC2
STC vs STC2
I didn't find any differences in the encoding except the condition code, and no differences in…
I'm seeing Cortex-A7 cycle-timing table here :
http://hardwarebug.org/2014/05/15/cortex-a7-instruction-cycle-timings/
For example,
VADD.F32 Dd, Dn, Dm takes 2 cycles
VADD.F32 Qd, Qn, Qm takes 4 cycles
same goes for VMUL..
Is this really the case…
The registers in the instructions are usually 'named' Rn, Rm, Rd, ...
Is there some deeper meaning in the names?
Usually Rd seems to mean 'destination register'
Sometimes Rn is the only operand, sometimes it's Rm. Also the place in the instruction…
In quite many instruction descriptions it says:
if d == 15 then UNPREDICTABLE;
What does this mean?
Can the instruction really work in some unexpected way in each such case or what?
I guess if I use a bit-reversing instruction on PC I should expect that…
In some instruction descriptions there are calls to SignedSatQ (directly or indirectly).
The pseudocode for SignedSatQ:
(bits(N), boolean) SignedSatQ(integer i, integer N)
if i > 2^(N-1) - 1 then
result = 2^(N-1) - 1; saturated = TRUE;
elsif i < -(2…
Hi,
I was using following method to read clock in cortex-a15:
static void readticks(unsigned int *result)
{
struct timeval t;…