• Locked L2 cache (Pl310) Write issue through JTAG- Zynq 7000

    Abhilash VR
    Abhilash VR

    We are using a Zynq-7000 SoC, and we are trying to do read and write to a locked L2 Cache through JTAG.

    From JTAG, Read works properly but writes makes the specific cache line corrupted,

    Step 1 : Initial Setup

         1. Wrote an application Which runs from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 CPU self-tests

    Daniel Watson
    Daniel Watson

     

    Hi!

    I am currently working in a project with a Freescale i.MX6 (Cortex A9) board. The system has to be certified against the ISO 13849 standard and my job is to implement software diagnostics in accordance to ISO 13849.

    Now my problem is that ISO…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cortex-A15 instruction set and optimization ways on this platform?

    Meng
    Meng

    Dear,

    I am an greenhand developer on cortex-a15.

    now I need some specification as follows:

    where I can get the instruction set of cortex-A15?

    are there some documents about optimization technology on cortex-A15(image processing optimization)

    Thanks a lot.

    …
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMP ARM cores hang when using DMA and two cores enabled

    Elad Nachman
    Elad Nachman

    Hi,

    I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

    I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

    SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

    The DMA transfer goes from…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • HI,why the VFP vector mode can not be used in cortex-a series processors?

    fansi
    fansi

    HI,why the VFP vector mode can not be used in cortex-a series processors?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Type 2 Hypervisor with Hardware Assisted Virtualization as Cortex A15

    Muhammad Faisal
    Muhammad Faisal

    Respected Experts,

                                  I would like to know that is it possible to get the advantage of Hardware Asssited Virtualization to develop a Type 2 Hypervisor which runs on …

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • TrustZone Controller in FVP Cortex57-A Base platform

    Xinwei
    Xinwei

    Hi,

    I start to learn and program TZC-400  in FVP Cortext57-A Base platform with DS-5, and encounter something that I don't understand.

    I start the FVP as non-secure mode by using the paramter "bp.secure_memory = false".  Then I poll TZC's  gate_keeper…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why does FPU performance differ in AArch64 and AArch32 with Cortex-A53?

    Yasuhiko Koumoto
    Yasuhiko Koumoto

    Hello experts,


    I have come to having a question.
    VFP Benchmark is a benchmark application which was made by a certain Japanese in order to measure ARM VFP performance especially for ARMv7-A and ARMv8-A.
    The software can be downloaded from the following link…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM v8 PMU Cycle counter

    B Ravikumar
    B Ravikumar

    All,

    When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:

    asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));
    
        sleep…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MOESI state encoding of Cortex-A7

    Isa
    Isa

    Hi,

    I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

    we can see several information regarding a cache line. Those are:

    1. Current data in cache

    2. its 4-bit MOESI state,

    3. Outer Memory Attribute

    4. its tag

    5. NS State.

    However…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Raspberry Pi 2 JTAG error on memory access

    Alessandro
    Alessandro

    Hi all,

    I am trying to connect to the RPi2 JTAG.

    I have the following setup

    - Raspberry Pi 2 running Raspbian 8.0 (Jessie)

    - OpenOCD 0.9.0 with a J-Link EDU connected to a Ubuntu system.

    I setup the GPIO in order to expose the JTAG interface and the…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why there are 4 cores per cluster in ARMV8 architecture

    RadarSong
    RadarSong

    Hi experts,

    I want to knows why there are 4 core cores per cluster in ARM big.Littte architecture?

    Is it possiable if we make more cores per cluster? if not, what is the limitation?

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • PL310 cache synchronization

    Vincent Siles
    Vincent Siles

    Hi !

    I am working with the PL310 L2 cache controller and I have a question about the "Cache Synchro" maintenance operation.

    - when I want to perform a synchronization, should I just wait for bit 0 (bit C) of the Cache Synchro register to be 0

    …
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A9 single core

    Vincent Siles
    Vincent Siles

    From the TRM of the Cortex A9 we can read in section 7.4.3 Cortex-A9 behavior for Normal Memory Cacheable memory regions:

    SCTLR.C=1 The Cortex-A9 Data Cache is enabled. Some Cacheable accesses are still treated

    as Non-Cacheable:

    • all pages marked as Write…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SIGILL in 32bit chroot on Cortex-A57

    Yichao Yu
    Yichao Yu

    I'm getting a SIGILL when running a ARMv6 program in a chroot environment.

    The instruction that triggers it is

    Program received signal SIGILL, Illegal instruction.
    0x000104f0 in f ()
    (gdb) disassemble $pc
    Dump of assembler code for function f:
    => 0x000104f0…
    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Performance effect because of removing some instructions from ARMv8?

    Natesh Raina
    Natesh Raina

    I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • reason for ARMv8 EDSCR err bit set

    Strong
    Strong

    Hi,

    I'm working on a project which is for debugging cortex-a53 through Jtag interface.

    The Jtag clock TCK is set to 300kHz which is pretty low, and I can properly read back debug registers such as EDSCR and EDPRSR. EDPRSR is 1 before I issue the 'halt…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is it necessary for ARM-v8 soc to flush L2 cache to DRAM ?

    RadarSong
    RadarSong

    hi :

    I know , we can flush L1 I/D cache items to PoU with kernel interface(flush_cache_*).

    however, I can not find any clue about flushing L2 cache to DRAM(if without L3). 

    and I saw some points that L2 flushing was not needed.

    for ARMv8,  how can…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any available data about the PPA comparison b/w Cortex-A7 and Cortex-A53

    Shane Yu
    Shane Yu

    Performance (DMIPS/CoreMark/SpecInt, etc.), Power and Area comparison on an apple-to-apple basis? Thanks a lot!

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to use the amba bus?

    Idan
    Idan

    Hello,

    i have the Zedboard which contains arm Cortex-A9 cortex with the amba bus..

    i have searched a lot but I probaly miss the point.

    i want to use data and to transfer  data from the processing system to the programable logic section via the amba bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Regarding mismatched memory attributes and cacheability

    Hemant
    Hemant

    As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ

    My question is specific to the case when it is only the cacheability…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why the address width of MMU-500 is different with Cortex-A53/57?

    wangyong
    wangyong

    I find the description below from MMU-500 TRM.

    Address width

    The incoming address width is fixed at 49 bits, where A[48] specifies VA sub-ranges. You must tie all unused bits to zero. The output address width is 48 bits and the width of the AC address

    bus…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARM have a time counter mechanism?

    Cyberman Wu
    Cyberman Wu

    Say, like Time Stamp Counter of x86, or Time Base of PowerPC, which can used to

    do some performance profiling.

    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Guidelines on reducing Cache Miss rate

    techguyz
    techguyz

    Hi Experts,

    Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

    If it is more specific to A/R/M then its great..

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Minimal Frequency of Operation

    techguyz
    techguyz

    Hello,

    Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
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