• Cortex-A9-PL310 AXI connection

    Luke
    Luke

    Hi experts,

    I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

    I think Figure 1.2 in the TRM is a good starting point:

    CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Armv7 ICIALLU vs ICIALLUIS

    Paul
    Paul

    Hi experts! I have a question about cache instruction.

    DDI0406C_b_arm_architecture_reference_manual for Armv7  says

    Effect of the Multiprocessing Extensions on All and set/way maintenance operations

    The only architectural guarantee for the following…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • what are the main differences between cortex A7, A9, A53

    aaa
    aaa

    What are the main/important features added/updated?

    Thank you.

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ordered-memory-access wait for response?

    loquat
    loquat

    Hi,

    I use Cortex-A17.

    Any question.

    -------------------------------------------------------------------------------------

    Example.1

    memory-type is device.

    1. LDR R0, [R2]

    2. STR R3, [R4]  (R2 != R4)

    On AXI-bus, (2.)write transaction is wait for (1.)read…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which processor has the most cores?

    Michael
    Michael

    Which arm processor has the largest number or cores?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Read allocate will impact bzero performance or not

    Ron
    Ron

    I'm trying to understand read allocate mode in cortex A7 core. From description of Read allocate mode in TRM of Cortex A7 core, my understanding is that bzero will downgrade memset performance while memset was done with consecutive memory.  For example…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to avoid bus error while using neon instruction vld2.32 on cortex a7?

    Katta Phani Kumar
    Katta Phani Kumar

    Hi, I am using imx6ul board which has cortex a7 processor. I am using ffmpeg .s files which has assembly code to integrate into our project to speed up the code.  Here is the ffmpeg code in the file mdct_neon.S.

    #include "asm.S"
    .fpu neo…

    • Answered
    • 9335.zip
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • NE10-Library -> FIR-Filter cycle counts: C-version faster than NEON-version?

    CFriebel
    CFriebel

    Hi,

    i'm currently trying to measure cycle counts for FIR-filtering with the NE10 library. I'm using a Raspberry Pi 2 with ARM Cortex-A7 running on Raspbian as a target.

    I activated the Cortex-A7 performance counter register to read out the cycles…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARMv7 Branch Prediction Enable

    Wang Feng
    Wang Feng

    On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed:

    ...

    @ Invalidate TLB

    MCR  p15, 0, r1, c8, c7, 0

    @ Branch Prediction Enable

    MOV r1, #0

    MRC p15, 0, r1, c1, c0, 0     @ Read Control Register configuration data…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • wrong reset value of TTBR0 at reset, in Cortex A9, R3P0

    anoop
    anoop

    Hi

    i have some questions on dual Core CortexA9 r3p0 revision.

    I am using Cortex A9 r3p0 processor in Our SOC(system on Chip). when i connect to Core 0 and read TTBR0 register i get 0x00004001, but when i connect to Core1 and do read the same TTBR0 register…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • a appropriate CortexA15 development board

    geekfolk
    geekfolk

    I am looking for a appropriate CortexA15 development board. If the price is less than $1000, or even $500, so much the better

    Does anyone have the suggestion with such board?

    Thank you!

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Multi Core and Boot Loader

    Victor Mehta
    Victor Mehta

    Would this group be able to answer some multi arm core and boot loader questions that we have ?

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SP805 Watchdog Timer

    Jam
    Jam

    Hi,

    I am writing a driver for watchdog timer for my custom platform, what I am observing is, as counter 1st time reaches to zero , then it generates an interrupt and ISR is called

    1. if I clear this interrupt in ISR then counter is reloaded and continue…
    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Problem with understanding memory barriers and problem of barriers taking too long time to execute in ARM Cortex-A15 corepack

    Arif Erman Kulunyar
    Arif Erman Kulunyar

    Hello community and experts,

    I am having a troubled time to understand the memory barriers. The further I read, the further I am being paranoid about the speculative reads and cpu re-ordering.

    I will have some questions and I will really appreciate any…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How many cycles requires the instruction QBNE?

    Alex
    Alex

    QBNE (Quick branch not equal)

    Using the PRU in the Beaglebone black (AM335x 1GHz ARM® Cortex-A8) I am asking how many cycles requires the instruction QBNE?

    qbeq myLabel, r1, 0

    I suppose two if the comparison is false: one is for compare and one is for…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex 32b/64b processors with Data Trace capability?

    Andreas Koch
    Andreas Koch

    Hello all,

    do any of the faster application processors (Cortex-A9 and up) have data trace capabilities enabled in their on-chip debug logic? I have been looking at both Xilinx and Altera Cortex-A9 cores, and both of them appear to only provide instruction…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Kernel page table makes page fault although other core already mapped.

    Yeo Reum Yun
    Yeo Reum Yun

    Hi, expert. I'm making CacheFlush function by Virtual Address.

    I'm using TTBR0 for user area, and TTBR1 for Kernel Area, and I'm using Dual core, Cortex-A9

    I'm using Cache Flush Policy as Write Through about Kernel PageTable (Below KPT) itself…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how should a FPGA engineer learn ARM based micro processors?

    vikasp
    vikasp

    Dear all,

    I am an engineer who is doing signal processing on xilinx FPGAs. I am familiar with C/VHDL/MATLAB. However I want to learn ARM based micro-processors. I know very little about processors and their architecture. Absolutely no practical experience…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why does the ARM A15 processor have so many DVFS levels ?

    Kiran Chandramohan
    Kiran Chandramohan

    For eg. the A15 on the Samsung Exynos 5422 has around 19 DVFS levels which varies frequencies from 200MHz to 2GHz.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to start ARM Programming???

    Praveen Ganiger
    Praveen Ganiger


    Dear All,

           I am new to Arm Processors, I don't know how to start Arm Programming and Application development, can anybody help me? I have working experience on DSP Processor, and Microcontroller, which is the best low cost Arm Processor for personal…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to get the secure(or non-secure) state on Cortex-A53?

    Brian Kim
    Brian Kim

    Could anyone give me the code to get the current secure state?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Using the whole Cortex-A L2 Cache without external memory

    Laurent
    Laurent

    I'm thinking about using a cortex-a7 in "bare-metal" where I don't need much memory, so i'd like to avoid using external memory.

    The CPU boots from an external 4MBytes SPI NOR FLASH chip.

    It has 512 KBytes of L2 cache and 32 KBytes…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • cortex A9 multi-core

    guqintai
    guqintai

    I'm learning cortex-a9 on freescale imx6 platform. How to start multi-core? And how to communicate between cores? I'm confused.

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • which ARM version that i should use for PLC

    houssam
    houssam

    hello !

    i am houssam an electrical engineering student, i am new to this forum and new for ARM processore i want to make my own PLC (programable logic controler), and i need a processore for to build this PLC, i find a lot of type of ARM processore (cortex…

    • Answered
    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Barriers in in-order cores like cortex-A53, A7

    oootha
    oootha

    Hi experts!

    As you know, power efficient arm like cortexA7, A53 has in-order pipleline.
    However as far as I understanding, Barriers like dmb, dsb, isb are related with out-of-order memory access.
    But barriers are even used in in-order cpus.
    What is for?
    Can…

    • over 4 years ago
    • Processors
    • Cortex-A / A-Profile forum
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