• Initial page table walk for secure/nonsecure accesses

    KamGators
    KamGators

    I have a basic concept question.  From what I read in the ARMv8 docs... there is an NS and NSTable bit in the page table entries themselves for the 2nd level and higher page table lookups.  So these can be used to block access ... I.e. NS access is attempting…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to Write CP15 registers (CRn:C15) in Non-Secure mode

    Paddu
    Paddu

    Some of the Cortex-A8 registers like CP15 registers (CRn:C15) are writeable
    only in secure mode. How to write these registers when the CPU is in Non-Secure  mode?
    Please let me know if there is any reference example code on this.
    The Cortex-A8 manual mentions…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Precise abort vs synchronous abort in armv7

    Saud
    Saud

    I am new to arm architecture. I am reading exception handling from ARM cortex-A series programming guide. I have confusion about the technical difference between precise abort and synchronous abort or imprecise abort and synchronous abort. Are they refer…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SPI VIP

    BSM
    BSM

    how to implement the daisy chain concept in SPI vip?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • SMP to suspend an individual core with security OS

    astonelin@gmail.com
    astonelin@gmail.com

    Hi All,

    a SMP architecture, like CA53-4core-mp, with a secure OS running at aa32 secure state.

    how to implement a suspend/resume flow on a individual core?

    TRM only mentions about how to clean cache and off-line from smp

    But how to do a cache flush through…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • why inner attribute is affected by outer configuration?

    geekfolk
    geekfolk

    Hi expert:

    I am configuring a CortexA15 system. In the  LPAE page table entry, SH[1:0] is configured as 11, so this is a Inner Shareable field. Then I need to set MAIR0.attr0  which is used by stage 1 translation.  The problem is, my system behave differently…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Which is better of thees CPUs

    kasem
    kasem

    Which is better of thees CPUs:

    Cortex A53 octa core 1.5 ghz,

    Cortex A7 Allwinner T8 Eight core 2.0 ghz,

    Cortex A9 Quad-Core 1.8 ghz ?

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A15 MPCore: How to Enable Monitor Debug Mode

    Melih Bayraker
    Melih Bayraker

    Hi experts,

    I want to enable monitor debug mode for Cortex-A15 MPCore. I tried modifying DSCR[15] bit but watchpoint event still won't generate exception/abort. Core was in no-debug mode before modifying the DSCR (after power-on). I know I configured…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • shareability attribute for armv8 cortex a-53

    MarekBykowski
    MarekBykowski

    Hi,

    I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

    My question is how should I interpret the shareability domain: inner, outer…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A7 - Boot from SPI NOR vs Execution In Place (XIP)

    ENRICO
    ENRICO

    Hi folks,

    I've been working for years with ARM -M processors and I'm facing -A processors for the first time.

    I fell in love with Allwinner's V3S processor which is v7-A type.

    The datasheet says that the processor is able to boot from an external…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Different performance in HYP and SVC mode ARMv7A?

    ivanpavic
    ivanpavic

    I'm doing some testing on Exynos5422 SoC which implements big.LITTLE architecture (A7 + A15), I'm running bare metal application which starts in HYP mode. I haven't returned from HYP mode by accident and then software delay which I implemented by simple…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Non-Cacheable memory and DMA on armv7a

    Vincent Siles
    Vincent Siles

    Hi !

    Consider a micro-kernel (not Linux) where device drivers are userland applications (PL0).

    We would like to use DMA based device, like an Ethernet controller for example. To this mean, the micro kernel allocate some memory to the user application…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ACP and DMA usage on A53

    leslielg
    leslielg

    Hi,

    I'm using DMA transfering data through ACP on A53. 

    According to A53 TRM, ACP burst size limits to 16B and 64B, does it mean the DMA connect to ACP also limited to transfer 64B data in max each time?

    Then software must re-configure DMA then re…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • A53 preload mechanism

    MarkL
    MarkL

    Hi,

    I am reading the A53 MP Core doc.

    My question is related to instruction preloading in aarch64.

    In case of a very large block of code with no function calls, I want to make sure the L1 cache is always filled.

    Question 1:  Will the PLI instruction first…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • MRS [A/C]PSR latency armv8-a?

    MarkL
    MarkL

    HI,

    Do anyone has a clue on the latency of the MRS CPSR (or APSR) command?

    I want to read the flags with no jump (and it is critical).

    Thanks

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Data synchronization Barrier and cache.

    Marcin.Kondraciuk@secom.com.pl
    Marcin.Kondraciuk@secom.com.pl

    Hi, everybody. I have system based on multiprocessors system with ARMv7-A. I need copy table from one point of memory to another. I use for this task DMA. Memory attribute is write-back cacheable. Before starting copy by DMA, I clean data cache by MVA…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A15 vs A73 speed Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz)

    MICHAL LAZO
    MICHAL LAZO

    I did some benchmark Odroid XU4(A15 1,8GHz) vs Hikey 960(A73 2,4GHz) 
    discuss.96boards.org/.../2140
    And I would expect better results
    but it looks like it is pretty much same if we have A15 on same frequency

    Anybody can explain this?

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is there any tool to profile power of a C code on Linux running on Cortex A53?

    B Ravikumar
    B Ravikumar

    We want to profile the power consumed by an application running over Linux kernel 4.2.x on Cortex A53. Is there any tool which can help here?

    regards,
    Ravi

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Programming TZASC in Secure Mode

    sarjoon
    sarjoon

    Hi everyone,

    I am working to setup the TZASC on I.MX6UL based dev platform platform.

    I did the following.

    - Running SPL bootloader from OCRAM

    - Disable the bypass (by setting GPR9's bit 0 to 1 on my boards).

    - Setup 2 regions

           * Region 0 - Base…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CP15SDISABLE

    AALLeeXX
    AALLeeXX

    Hello,

    it maybe not the right place to ask, but friends on PI forums seem not aware either so, i ask here in case;)

    The question is simply, where is this input mapped on the raspberry PI2 ? Is it a conventional input ? Is it really mapped or implemented…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • is there any simulator for ARM CORTEX A series

    dhrumil Shah
    dhrumil Shah

    I was working on smart wearable using ARM Cortex A series so there is any other simulator for ARM CORTEX A

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to execute 32-bit ARM assembly in a 64-bit environment

    sandrosart
    sandrosart

    Hi everyone,

    I have a 32-bit arm assembly program and I'd like to run it in a 64-bit os (in particular, in a raspberry pi 3 board). Which libraries do I need in order to do that?

    Thanks in advance.

    Sandro

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Memory read error at 0xF8000008: Cannot read write-only register.

    doner_t
    doner_t

    Hello, 

    I am not sure, here is correct place to ask this question. But I want to try ; 

    I have received an error :  Memory read error at 0xF8000008: Cannot read write-only register, When I try to debug a basic memory test code, in CortexA9.  I can not even…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

    thomas_cp
    thomas_cp

    Hi, 

    I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

    The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

    There is no L3 cache. So the memory…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A53 : Cache policy setting

    PrabhuKrishnan
    PrabhuKrishnan

    Hi,

    Can somebody help me to understand how the cpu will set the cache policy to the transaction? Is it configured by any processor or descriptor? 

    I'm enabling the caching using the SCTRL register and in the MMU configuration table, I'm setting the memory…

    • Answered
    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
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