• What's the difference between core, processor,cluster and CPU in ARM architecture?

    Grady
    Grady

    What's the difference between core, processor,cluster and CPU?

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A8 : Enabling D Cache aborts

    Gopu
    Gopu

    I am using Omap3515 (Arm Cortex A8). Enabled I-Cache, D-Cache, Branch Prediction and MMU.

    I am getting a data abort, if I try to copy a frame buffer of 600KB from an external memory region to another external memory region. After the data abort, I could…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A7 Processor DSP

    Акоб
    Акоб

    Hello everyone.

    I am new usage of Allwinner A20.

    I read in Cortex-A7 specification, that it have DSP & SIMD extensions.

    And if there are digital processing unit in processor, can i use it? Can i drop on it some code, as any other DSP? And if yes, will…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How many states for an ARM Cortex A8?

    Robert
    Robert

    Hi,

    When I read about Thumb2 instructions, I have such a question: How many states for a Coretx A8? I know it has ARM and Thumb states. Thumb2 instruction is belong to Thumb state? Then does A8 have a pure Thumb instruction besides Thumb2 set?

    Thanks,

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • What type of ARM is used in 10-Gb Ethernet chip?

    Robert
    Robert

    Hi,

    I heard that some 10-Gb Ethenet chip embedded an ARM core. I am curious about what type of ARM (A, M or R) is embedded in such a high speed Ethernet ASIC. I feel that it may be a R series ARM. Is it right? Due to such a high speed data rate, what chip…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Is the 'S' necessary in the asm code?

    Robert
    Robert

    Hi,

    Before I write some Cortex A8 assembly code, I review some disassembly code of a small C program. In the following snippet, I don't understand the necessity of 'S' in ADDS. In fact, I don't see the usefulness of the whole line of

    ADDS…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM SPEC score.

    Mazen Ezzeddine
    Mazen Ezzeddine

    Dear All,

    Does ARM  offer any official/reliable  SPEC2000/2006 benchmark results for  A15 cores? I am running some experiments and need to make comparisons.

    Thank you.

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Reset Management Register Functioanlity in ARM v8

    techguyz
    techguyz

    Hi Experts,

    Does the Reset Management Register will be implemented mandatory or optional for the SoC based on ARMv8 and how it is practically used ?

    Regards,

    Techguyz

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Invoking application from Hypervisor in ARM V8

    techguyz
    techguyz

    Hi Experts,

    Does it possible to invoke the application running in EL0 directly from the hypervisor EL2 without giving control to EL1 ?

    Regards,

    Techguyz

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Integrated Debug Functionality in ARM v8

    techguyz
    techguyz

    Hi Experts,

    What are all the list of integrated debug functionalities in ARM v8 which will be affected by the cold and warm resets.

    Regards,

    Techguyz

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ldm/stm with not aligned 4byte

    Paul
    Paul

    Hi experts!

    I want to use ldr/str or ldm/stm to copy memory not aligned 4bytes.

    I know their input address should be aligned by 4 bytes.

    but is there any solution to use ldr/str or ldm/stm though src or dst isn't aliged 4byte by modifing following code?…

    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • CA72 transactions IDs

    Jay Zhao
    Jay Zhao

    In the TRM of CA53, I see some descriptions of the encodings for AWIDM and ARIDM, and it's quite clear to distinguish Read & Write transactions from different cores.

    But in CA72, I can't find such descriptions.

    In my simulation, tt seems that…

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM Cortex A9 flush cache

    Tamilselvan Shanmugam
    Tamilselvan Shanmugam

    I'm measuring worst case execution time of an application. I would like to flush L1, L2 (Instruction and Data) cache and then begin my measurements.

    Is it doable from user mode?

    Processor: ARM Cortex A9

    OS: Linaro Linux

    • Answered
    • over 5 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A8 - accessing banked registers from monitor mode

    Jitesh Shah
    Jitesh Shah
    Note: This was originally posted on 20th March 2012 at http://forums.arm.com

    Hi Group,
    I am working on a Cortex A-8 Processor (ARMv7-a architecture). I am in the monitor mode and trying to access SP of the SVC mode.

    I know two ways I can do it:

    1) Using the…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Sampling/tracing memory addresses

    chansen3
    chansen3

    Is there any ARM tool that will sample or trace addresses of memory accesses for a processes?  And specifically for a Cortex A72-A.  It appears that there is support for this with the Statistical Profiling Extension or an Embedded Trace Macrocell, but the…

    • over 3 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • how to understand L1 cache but L2 & L3 non-cached

    phil9980
    phil9980

    A5.6.6 Memory Behavior
    The Cortex-A55 core supports all the ARMv8 memory types.
    However, the following behaviors are simplified and so for best performance their use is not recommended:
    Write-Through

    Memory that is marked as Write-Through cannot be cached…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Issue with WatchDog reset De-asserting

    BAB
    BAB

    Hi,

    I am working on ARM CortexA9 processor. I could able to enable both l4wd0 and l4wd1 watchdogs. Issue is system is resetting but not rerunning. I tried changing the register values of reset Manger as well.

    How to de-assert the reset and make the system…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Watchdog timer not entering ISR

    sherry
    sherry

    I am using ARM cortex A9 core in Zynq. I want to trap any bugs in hardware or my firmware. I intend to use watchdog module in interrupt mode and connect it to Global interrupt controller (ScuGic). When the watchdog counter decrements to zero, it is to…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Binary Semaphore upset by FIQ

    LdB
    LdB
    semaphore_take:   

        mov    w2, #1                 // LOCK value
        dmb    sy                     // ensure all observers observe data before aquire is attempted
        ldaxr    w1, [x0]             // attempt to read and aquire lock
        cbnz    w1, semaphore_take    // lock is not zero so loop and try and aquire again
       
    …
    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex-A8: memcpy() into DMA buffer hangs on NEON instructions

    LeonP
    LeonP

    I am cyclically filling the mmap-ed DMA buffer with my data by copying it from "normal" memory in 290 bytes chunks.

    At the first cycle memcpy always passes OK. At the second cycle it hangs in __memcpy_neon routine (at least this is what the…

    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • CPUACTLR_EL1 and S3_1_C15_C2_0 in Cortex-A57 TRM

    chinatiger
    chinatiger


    hi, experts: 

    In Cortex-A57 TRM chapter 4.3.66 :

    It defines CPUACTLR_EL1 register, but this register name is not CPUACTLR_EL1.

    Its name is S3_1_C15_C2_0.

    Why?

    best wishes,

    hi

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • How to read PMU correctly for multi-thread on dual core Cortex-A9 under userspace

    yunwu
    yunwu

    Hi,

    I have enabled the userspace pmu access by building a kernel module for both core on Cortex-a9. Then I follow the standard procedure of pmu counting:

    1. Disable performance counters

    2. Set cycle counter tick rate

    3. Reset performance counters

    4. Enable…

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • ARM: 743626—An imprecise external abort, received while the  processor enters WFI, may cause a processor deadlock

    Manyam
    Manyam

    Can someone explain more about this issue, and please provide the fix for this issue.

    • Answered
    • over 6 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does ARMv8 SOC support cache lockdown?

    chinatiger
    chinatiger

    hi, experts:

    In ARMv8 Arch reference manual, it said:

    ARMv8 supports cache lockdown feature, but it is implementation defined.

    So, my question is:

    Has the integrated L2 Cache controller some registers related lockdown feature settings?

    I didn't find them in…

    • Answered
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
  • Cortex A8 Instruction Cycle Timing

    barney vardanyan
    barney vardanyan
    Note: This was originally posted on 17th March 2011 at http://forums.arm.com

    Hi) sorry for bad English

    I need to count latency for two instruction, and all I have is the arm cortex A 8 documantation(charter 16) !
    but I have no idea how can do this work…
    • over 7 years ago
    • Processors
    • Cortex-A / A-Profile forum
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