MOESI state encoding of Cortex-A7

Isa

Hi,

I am looking at Cortex-A7 TRM, In "Direct Access to Internal Memory"

we can see several information regarding a cache line. Those are:

1. Current data in cache

2. its 4-bit MOESI state,

3. Outer Memory Attribute

4. its tag

5. NS State.

However…

Answered

Cache cleaning and invalidating in ARM Cortex-A

Manyam

Cleaning or invalidating the L1 cache and L2 cache will not be a single atomic operation. A core might therefore perform cache maintenance on a particular address in both L1 and L2 caches only as two discrete steps. If another core were to access the…

Answered

Why A9 is multicore by A8 doesn't

techguyz

Hi Experts,

Which factor in processor decides whether it can be used in multi-core or not ?

Like as per my understanding A8 is used in single core whereas A9 is used in multi core. So which distinctive feature in A9 favors the multi core application ?

Answered

General Feature of Cortex processors on cache coherency

techguyz

Hi Experts,

Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?

I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…

Answered

VMSAv8-64 and spinlock

Ciro Donnarumma

Hi,

I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.

I'm writing bare-metal code, without…

Answered

shareability attribute for armv8 cortex a-53

MarekBykowski

Hi,

I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.

My question is how should I interpret the shareability domain: inner, outer…

Answered

Why linux set memory as inner shareable in multi-cluster ARMv8 cores?

thomas_cp

Hi,

I have board with two clusters, one has 4*A57 cores, and the other has 4*A53 cores.

The A57 cluster has its own L1 and L2 cache, A53 cluster also has its own L1 and L2 cache. Between the clusters there is a CCI.

There is no L3 cache. So the memory…

ARMv7-A: Cache maintenance operation by VA, performance

Niklas

Hi,

according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…

Answered

Cache and store buffer maintenance in cortex-a8!

Hamed

Dear All,

Technical data sheets for the ARM7500FE and ARM7100 say that:

"In the ARM Processor the cache will be searched regardless of the state of the C bit, only reads that miss the cache will be affected."

Now the question is that whether…

Answered