Hi,
I have a system with a multiple quad core clusters with Cortex A-53 and the CCN-512. L1 through L2 are integrated caches where L3 is an outer cache in 8xHN-F of the CCN512.
My question is how should I interpret the shareability domain: inner, outer…
Hi,
according to this talk, cache maintenance should always be performed by VA and not by set/way except during boot or shutdown. However, invalidating/cleaning a block of data by VA requires a loop to run over the entire memory block (in steps equal…
Greetings ARM community,
I have been tasked with cache maintenance. The necessity popped up because of DMA issues on USB.
As a quick (not perm solution) I used the invalidate all routine. While obviously not nominal in anyway
it does allow me…
