Hello,
I have run two different bare-metal programs on two corresponding ARM cores in Cyclone V (Cortex-A9) in DS5 using JTAG line. The SDRAM is shared between the two cores as is evident from the cache settings which is set to "shared" by default. Core…
Hello,
I am using a quad-core Cortex-A7 (on Raspberry PI 2). I run a Linux on Core 0,1,2 and a baremetal application on Core 3. My goal is to protect the baremetal application from the rest (i.e., the linux side). Initially I thought that I can do this…
Hi,
I'm trying to implement a spin-lock to synchronize the execution of all cores Cortex-A53 on my Xilinx-ZCU102 board, but I have some issues maybe due to a wrong configuration of the VMSA and cache coherence.
I'm writing bare-metal code, without…
I am working on an Arria10 SoC which has dual ARM Cortex-A9 MPCore. And I work on bare-metal environment with Intel SoCFPGA’s hardware library(HwLib).
On the shared SDRAM, I am planning to have dedicated memory regions for each core, and a shared…
Hi everyone,
Wherever I go on internet, the thing I read is that when SMC instruction is executed an exception is generated, it takes you to the highest exception level (EL3) where secure monitor is running.
In ARM v8 vector table, given on ARMv8-A architecture…
