• Debugger cannot execute cast and vectorization commands

    Rei
    Rei

    Hello. I am a novice in programming. I have a problem with the debugger.
    My target CPU is Cortex-A72 Aarch64, FPU Armv8 (Neon). I use vectorization.
    When the debugger reaches the line:
    uint8x16_t aa = vmovq_n_u8 (0);
    he writes that it is running, but nothing…

    • 9 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • What is difference between DCCIMVAC and DCIMVAC?

    Austin0101
    Austin0101

    The DCIMVAC represents a cache invalidate work. But one specific remark is that it will clean the data if the data is dirty before invalidation. Refer to followings

    /******************************************************/

    6.2.4 Data cache maintenance…

    • 10 months ago
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    • Cortex-A / A-Profile forum
  • -

    Hamed
    Hamed

    -

    • 10 months ago
    • Processors
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  • Synchronization Between CortexA and CortexM

    M.Eladouly
    M.Eladouly

    Hello,

    I'm working with a bare-metal application running on i.MX8 (QuadCore CortexA35 & Single Core CortexM4).

    Currently, I use Load/Store executive assembly instructions along with memory attributes for the MMU to synchronize between the CortexA…

    • Answered
    • 10 months ago
    • Processors
    • Cortex-A / A-Profile forum
  • Arm64 Long Format Translation Table Walk

    angeld
    angeld

    Hi all - I'm trying to understand stage 1 translation.

    Assuming that the translation is starting at level 2, how do you determine the number of page table entries in the level 2 table? The documnetation says it can have up to 512 for 4kb granule size…

    • 11 months ago
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  • compiler optimization options for ARMv8 GCC compiler on ARM cortex a53 (bare metal application)

    khan777
    khan777

    I am using ARMv8 GCC compiler(aarch64-none-elf-gcc) for my bare metal application on ARM cortex a53. I am using neon intrinsics with plain C in my code so I would like to ensure to use all optimization option available for this compiler.

    I tried -mfpu…

    • 11 months ago
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  • How Can I jump from EL1 to EL0 in bare metal environment

    Awax
    Awax

    Hello,

    I am working with a port of FreeRTOS on Arm64 soc , which is running at EL1, my goal is to perform a function call that will execute in EL0,

    I have come to understand that the only way for the EL switch is to set the correct M bits of the spsr_el1…

    • Answered
    • 11 months ago
    • Processors
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  • Unusual time in booting secondary cores on ARMV8 platform (Zynq MPSoc)

    Saud
    Saud

    Hi all,

    I am working on UltraZed-EG Starter Kit and trying to boot secondary A53 core from primary A53 core with an SMC call with 0xc4000003 as the identifier. I have measured the time taken to reach the entry point of secondary core and surprisingly…

    • 11 months ago
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  • Permission fault, level 2 on MMU enable

    jcal93
    jcal93

    Hi ARM folks, hoping someone can show me where I'm going wrong programming the MMU. The ESR_EL1 reports that it is a Permission fault, level 2. Here's what I'm trying to accomplish:

    4GiB space, 4kiB granule flat identity mapped, divided like…

    • Answered
    • over 1 year ago
    • Processors
    • Cortex-A / A-Profile forum
  • Does MSR DAIF require ISB instruction? If no, why?

    scopichmu
    scopichmu

    Dear experts,

    I see a lot of code in opensource like

    .macro disable_daif
         msr     daifset, #0xf
    .endm
    


    and it doesn't apply ISB instruction after it. Though I read in ARM manual that:
    "context-changing operations
    that require the insertion…
    • Answered
    • over 1 year ago
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  • EDSCR err bit set after a write to EDITR

    kka
    kka

    Hi,

    I have a very similar question to the resolved entry "reason for ARMv8 EDSCR err bit set".

    So I try to follow that to give the state information.

    Cortex-57

    JTAG TCK = 3,788MHz.

    ARM_STATE_AARCH64 is set

    Before Halt state:

    EDPRSR = 0x1

    EDSCR…

    • Answered
    • over 1 year ago
    • Processors
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  • Why does Arm still support short descriptors?

    DarkDante
    DarkDante

    What I'm asking is ARM Architecture Reference Manual for ARMv8-A  says in AArch32 there are two translation table formats:

    • Short descriptors: 32 bit
    • Long descriptors: 64 bit

    On page G4-4726 (Issue B.b), there are various points listed that each…

    • Answered
    • over 1 year ago
    • Processors
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  • What can cause getting Cortex-A55 DSU P-Channel PACCEPT/PDENY signals fail?

    Emmy0
    Emmy0

    Hi experts,

    I do an experiment about cpu power with a board which has 4 cores of Cortex-A55.

    I try to power on/power off core1~3 parallelly.

    Sometimes Both PACCEPT and PDENY are zero after changes the power state.

    If I only power on/power off one core,…

    • Answered
    • over 1 year ago
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  • [ArmV8] [Cortex-A53] [PMU] PM_CCNTR to measure cpuload

    Amr Fawzy
    Amr Fawzy

    Dear Experts

    I am working on a target that contains quad A53 cores operating at 1GHz. The operating system idle loop contains WFI inline assembly instruction. I know that the Core Clock halts during the WFI instruction which can be seen on the PM_CCNTR…

    • over 1 year ago
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  • The "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ?

    alexn
    alexn

    Hello,

    What exactly is the "usage model" of ARMv8 SVE contiguous "non-fault" load instructions ?

    I understand the usage model of "first-fault" SVE instrcutions (which is described in many white papers) but the "usage model" of ARMv8…

    • over 1 year ago
    • Processors
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  • System Frequency for CortexA35

    M.Eladouly
    M.Eladouly

    Hello,

    For a CortexA35, when reading the system counter clock frequency CNTFRQ_EL0, I found out that the frequency is 8 MHz.

    Is this normal? For a target running in GHz?

    The target is i.MX8QXP (Quad-Core CortexA35).

    • Answered
    • over 1 year ago
    • Processors
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  • What are the necessary preconditions to load a guest into EL1 from EL2?

    Branden Sherrell
    Branden Sherrell

    I have successfully moved from EL3 to EL2. After doing some initialization I am trying to move from EL2 into EL1 with a very simple guest image. My process looks like:

    • Map EL1 memory into EL2
    • Copy EL1 image to RAM
    • Initialize sctlr_el1 = 0x30d00800
      …
      • Answered
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • Setting PC for and waking up secondary cores from the primary core

      Branden Sherrell
      Branden Sherrell

      Given a multiprocessor system, how are the PC values of secondary cores set from the primary core? I've read lots of threads stating it can be done but without any details. I could not find anything in the ARMv8 reference manual.

      One might contrive…

      • Answered
      • over 1 year ago
      • Processors
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    • Difference between ARMv8 Data Abort exception subtypes "Not in translation table" and "Translation table fault at level"?

      Branden Sherrell
      Branden Sherrell
      I've gotten virtual memory working on ARMv8 after crafting the page tables. Oddly, _most_ of my translations are working (identity mapped) save for Flash which sits at physical address zero. I use a single function that edits the page tables, so the fact…
      • Answered
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • ARMv8 memory ordering

      roffelsen
      roffelsen

      In the ARM Architecture Reference Manual issue D.a (ARM DDI 0487D.a) section K11.3.1 "Acquiring a lock" has the following example code:

      AArch32 
      Px
              PLDW[R1]                     ; preload into cache in unique state
      Loop
              LDAEX R5, [R1]               ; read…
      • Answered
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • Getting Execution Time of progams on armv8_64-bit processors

      abhi.verma
      abhi.verma

      I have written a library for ARMv8-A 64 bit processors (OS- linaro debian). Now I want to time them. I am utilising gcc compiler and on Intel processors I was timing the execution utilising std::chrono high resolution clock. The issue with arm is, it…

      • Answered
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • Obtain CPU Temperature in Kernel

      zzT
      zzT

       Dear All,

      I am using a raspberry pi B+ that uses a Broadcom BCM2837 SoC with an ARMV8  processor. I want to get the cpu temperature in a Linux kernel file. Like in x86, I can use rdmsr_on_cpu function to load the temperature from MSR_IA32_THERM_STATUS register…

      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • What is arrangement specifier(.16b,.8b) in ARM assembly language instructions?

      surajrgupta
      surajrgupta

      I want to what exactly is arrangement specifier in arm assembly instructions.

      I have gone through ARM TRMs and i think if it is size of Neon register that will be used for computation

      for e.g. TBL Vd.Ta, {Vn.16B,Vn+1.16B }, Vm.Ta

      they mentioned Ta to…

      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • ARMv8 PMU access

      Jorge
      Jorge

      Hey guys,

      I'm running a sw in a multicore ARMv8 system and I'd like to know a bit more about the PMU component. There is a PMU per CPU, right? 

      Is it possible from one CPU to access the other CPU's PMU using the memory mapped interface?

      …
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
    • determine a page size on armv8

      MarekBykowski
      MarekBykowski

      Hi,

      I have a need at determining a page size, particularly for a Non-secure EL1, stage 1. I know of 

      __asm__ volatile ("at s1e1r, %0" : : "r" (buf));    
      __asm__ volatile ("mrs %0, PAR_EL1\n" : "=r" (par_el1));

      …
      • Answered
      • over 1 year ago
      • Processors
      • Cortex-A / A-Profile forum
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