how to know the specific cycles of every arm instruction (armV7,cortex-a8) while executing in asm form?

if there are some documents which describes it in detail?

In Chinese:

我目前用cortex-A8（armV7）来开发项目，由于一些算法需要在ARM端跑，算法需要优化，需要写arm汇编指令，

想知道，armv7每个指令执行消耗的周期…

Hello Everyone,

I am new to ARM processors.  I am trying to get a good handle on the low levels aspects of the ARM processor like exception handling.  From searching the ARM website and looking at the data abort handler documentation I am pointed to this…

Hi,

I am trying to bring up CPU1 on ARM v7 architecture  (assume CPU0 already bring up & set c-environment)

using below code, but it hitting with error: "stack smashing detected"

ldr  sp, =cpu1_stack

b start_task2

* cpu1_stack define…

Hi experts! I have a question about cache instruction.

DDI0406C_b_arm_architecture_reference_manual for Armv7  says

Effect of the Multiprocessing Extensions on All and set/way maintenance operations

The only architectural guarantee for the following…

Hello All/ARM,

I would like to know if there is any way of process to hang a specific core for certain duration of time? Either from Kernel/User space? Also i have trying to understand if that is possible or not?

Correct me if something is there already…

On "ARM Cortex -A Series Programmer’s Guide" , a piece of code is followed:

...

@ Invalidate TLB

MCR  p15, 0, r1, c8, c7, 0

@ Branch Prediction Enable

MOV r1, #0

MRC p15, 0, r1, c1, c0, 0     @ Read Control Register configuration data…

hi, expert

i study ArmV8 architecture.

  On taking an exception to a higher Exception level, the Execution state either:

    • Remains unchanged.

    • Changes from AArch32 state to AArch64 state.

  i konw that…

Since I am currently reading lot of ARM documents to understand the architecture as a whole, I request you to mention as to what happens in case of CORTEX-A processor in the nested interrupt handler implementation since we have a SPSR in CORTEX-A processors…

For a TrustZone enabled processor, what if a normal world application (e.g. 3rd party application) directly uses SMC instruction to request a secure world entry? In a typical case, it it a responsibility of monitor SW or Secure OS kernel to authenticate…

HI,why the VFP vector mode can not be used in cortex-a series processors?

All,

When I am using the cycle counter in AArch64, I am not getting cycles properly. I have enabled read of pmccntr_el0 in user space using a small kernel module. I have sample code like:

asm volatile("isb;mrs %0, pmccntr_el0" : "=r"(prev));

    sleep…

I was going through the ARMv8 Architecture Reference Manual and I came to know that it does not support many instructions that were previously supported by ARMv7 architecture. For example ARMv8 does not support conditional codes and have a seperate instruction…

Hello,

Is there any data regarding the minimum and maximum frequency a processor can operate in ARM V-7 ?

Hi All,

I could understand the difference in ARM V-7 processor differences between A/R/M.

But does the clock cycle per instruction value for the various series of processors (A/R/M) remains the same or similar, assuming the data fetch and instruction fetch…

Hi Sirs,

I got a question about the way Linux 3.18 defines the "writel()".

In linux-3.18/arch/arm64/include/asm/io.h, it describes:

/*

* I/O memory access primitives. Reads are ordered relative to any

* following Normal memory access. Writes are…

Hi there,

I have been going through a lot of ARMv8 documents, and I have a very basic question:

-Can I take a Linux Kernel, compiled for a ARMv7 device, and run it on an ARMv8 device in Aarch32 execution mode?

( Lets assume that the two SOCs are identical…

Hi Experts,

Is there any document on general software guidelines in reducing the cache miss rate in the system for ARMV7 architectures ?

If it is more specific to A/R/M then its great..