Basically I want to provide delay of 15 clock cycles  for writing and reading through axi4 bus .Is it possible?

Hello Ashley,

      I have couple of basic doubts w.r.t ACE-Lite Slave.

      The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…

Hi,

Was going through AXI spec.

As per AXI spec:

"AXI3 supports burst lengths of 1 to 16 transfers, for all burst types."

"AXI4 extends burst length support for the INCR burst type to 1 to 256 transfers. Support for all other burst types in…

Can an ACE master have multiple write channels ?

e.g. AW_0, AW_1, W_0, W_1, B_0, B_1, AR, R, AC, CR, CD

Can this still be considered as an ACE-compliant component ?

Hello:

    Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte  slave0 has…

AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??

Hi folks,

The technical reference states that only a subset of possible AXI transactions are actually generated.

This is described in http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0388f/Babiaggf.html

What happens for this table if the master…

Hi guys,

I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus.

First consider an unaligned access on address 0x1.

Can this access be created in 2 ways?

1) Addr=0x0, Wrstrb=1110

2) Addr=0x1, Wrstrb=0111

In the second…

Hi AXI-experts,

Does AX4 support burst sizes larger than the bus width?

Narrow transactions are allowed, but do wider transactions also work?

Best regards,

Robert

Hi guys,

I'm new to the AXI ecosystem.

However, I have one question related to unaligned read transfers.

Does AXI4 support unaligned read transfers although er are no strobe lines?

If so, which data on the bus is written?

To make it easier, discuss it…

I have bunch of questions related to AXI. Can someone help me by answering those?

AxSize can be varied across multiple transactions?

whose duty is to set byte strobe in a transfer? Is it the master which should generate byte strobes along with un-aligned…

Hi,

I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect.

1) In parallel, Can i have transfers(burst) to m1->s1, m2->s2 on write data channels? A-data form M1,  B-data…

Can someone explain me the advantage of having decouple write address, data channels in AXI4?

In AXI3 with data interleaving we can have multiple masters sending data to various clients but in case of AXI4 we don't support interleaving so how decoupled…

I wonder whether the read/write data channel handshake must occur or assert after the address channel handshake completed?

For example the master device will wait ARREADY assert or ARVALID dessert, before assert the RREADY?

Remark:

Just now, I noticed that…

Hi All,

Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

Thanks

Hi.,

As we know that there is a MakeUnique transaction in ace protocol, can anyone tell me how we can initiate this transaction..? I mean what is the respective signal in AXI4/ACE that allows us to set a master to initiate this MakeUnique transaction.…

Hello,

in the AXI4 specification I didn't find anything mentioned about width restrictions for the address signal. I'm currently trying to simulate a component which I wrote in VHDL which provides an AXI4 Slave interface. The BFM I'm using to simulate…

Hello Everyone,

Can someone explain the use cases of AxPROT? I am not fully clear on how to use these bits in a system. (So i would like to hear some use cases for this port)

Also, Please provide some info on how to set AxPROT[1] (How the system will distinguish…

Hello Everyone,

[This not specific to AXI3/4] Can someone give an example on how write data interleaving works? Is it used only when we have multi-master cases? or its possible with single-master cases also?

In case if we have 2 burst transfers with A …

Hi  there,

I have question regarding handshaking in the AXI protocol.Currently i am designing  decorder for AXI4-Lite master .

While doing the write adress  transaction, AWVALID  depends upon write enable.AWVALID is high when write enable signal…

Hi, anybody explain how data  is routed in interconnect? As stated in AXI4 spec, only start address issued from master,then how it is done in case of burst transaction? Please Explain how this is done.

HI there,

I have question regarding transaction in AXI4 bus (or any other bus). What happens  in write any read action when data transaction (handshaking) occurs before  address  transaction (handshaking) ?

Will the data be written to the…