Hi everyone! Please help me.. i have  a project with a custom axi slave  design that  implements multiple memory ranges 256 words each . A master ( my processor in figure) can write burst data to the example slave and read the data back. The problem is…

Hi,

  What is real time application of AXI exclusive access.

  Is it necessarily to do Exclusive read first then exclusive write.

  May i know the reason is it so?

There is a statement 'For wrapping burst, the length of the burst must be 2,4,8 or 16 transfers.' in AXI Addressing option.

I cannot understand that why must be 2,4,8 or 16 transfers? Is there some design issue?

Hope someone can help,thank you…

Hi, I am looking for a memory controller for AHB, dual (or multi) channel.

I found one in the ARM site but for AXI.

Thank you

Hello....!!!

Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

Hello,

I am working on Cortex-A53  and using Cortex-A53 DSM Model in my design. We are getting Data Abort exception on a read to ROM address and ESR_EL3 register showing its a DECERR External error. MMU and Cache both are not enabled at this point where…

Dear sirs,

I read ACE specification and ARM processor documents for ACP explanation. I always have some questions about ACP.

As soon as you know, ACP exists in SCU for data coherency.

Q1: The document says that ACP usually connects to a DMA or cryptographic…

i want to design a bridge between APB  and AHB in verilog

my design consists of :

1. control clock unit (ccu)   // using APB

2. my DUT contains registers module & functional module  // using AHB

3. tow memories (source memory and…

Hello ,

i can see that AXI have some bits : AWID ARID BID ARID RID , those bits role is trasaction ordering , well i want to know how axi form those bits , i heard (i dont know if it is true) that a master can use those bits to find his path to the slave…

Hi,

I am experiencing A complete arm core hang when both of the cores are employed in SMP mode and using DMA.

I was tested with Linux kernels 3.10, 4.1 and 4.6 in SMP mode.

SOC used is Altera Cyclone V SOC-FPGA with dual Cortex A9.

The DMA transfer goes from…

Hi all,

I was trying to extract this information from the AXI specification but I didn't find any clear answer.

I wonder how should an AXI component behave if an input xREADY signal is never asserted.

Example 1: a master starts a write transaction by…

Does anyone know of an Idiot's Guide to this topic? In particular, how does a processor with no special I/O instructions issue a request, e.g. to a serial output device to output "Hello, World"? And how does Memory-Mapped I/O work in detail? Where is…

Hi,

I have multiple questions related to multi-master AXI4 system. Eg: lets say we have 2 masters(m1,m2) and 2 slaves(s1,s2) and an interconnect.

1) In parallel, Can i have transfers(burst) to m1->s1, m2->s2 on write data channels? A-data form M1,  B-data…

Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.

Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.

Register slice is described in AMBA 3.0 AXI.

"This makes…

Hi,

    i am confusing in the following point ,with an example....

   if

     Start_Address = 23

     Number_Bytes = 8

     Burst_Length   = 8

     data_Bus_Byte…

Hi All,

Does ARM support pipelining flops in between valid/ready signals?Can someone explain why its *not* possible?

Thanks

I would appreciate assistance on the following:

Suppose a bus master with 128bit data width.

This master access a 64bit slave via AXI matrix as follows:

awaddr = 0x4000_909F

awsize = 0x0 (8bit write)

awlen  = 0x0 (single trans)

wstrb   = 0x0080;…

Hi,

I am seeing an issue, where the READY signal's assertion depends on the VALID signal. If the VALID signal remains asserted through out the transaction (Say, for a burst transfer), then for the second burst beat to occur, the WREADY should have been…

hey,

How to modify the value of AWCACHE [3:0] and ARCACHE[3:0] in AXI?

in baremental driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x00,

but in linux driver ,the default value of AWCACHE [3:0] and ARCACHE[3:0] is 0x01,

can anybody tell me…

Hi experts,

I would like to know more about the interconnection between Cortex-A9 and the PL310 L2 cache controller.

I think Figure 1.2 in the TRM is a good starting point:

CoreLink Level 2 Cache Controller L2C-310 Technical Reference Manual: 1.2. Typical…

Hello,

I don't know whether this question has been asked or not. If yes please direct me to the appropriate discussion.

My question is:

1. Suppose there are two masters, M0, M1 and one slave, S0. M0 initiates an Exclusive access to S0 and gets the response…

Hello,

I have a question on axi read time. If we have 20 read commands, the read outstanding is 4 and read latency is 500ns, how much time is needed to read all of these data back?

I feel puzzled on this for a long time and I need a relatively accurate…

Hi All,

       1)  1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…