Hi All,
I have a question on AMBA5 AHB feature : Stable_between_Clock property
The AMBA5 AHB Specification describes:
Signals that are described as being stable are required to remain at the same value when sampled at different rising clock edges in an…
I have a shared memory in DDR --- shared between two separate ARM execution environments (say A and B) in a heterogeneous compute SoC.
SW on each execution units (A and B) Reads and Writes to this shared location (imagine a array/matrix that…
Hi,
I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.
Let us assume EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…
if i want to read 16-bytes from 'hxx00 address(32-byte aligned address) on a 32-byte width data bus, what should be the arsize[3:0]? i donot want to put arsize='h5 as it would result in a performance penality if the slave is DDR controller.
Hi All,
This question is regarding "ReadNoSnoop" transaction of AMBA- ACE protocol.
If "ReadNoSnoop" transaction is used in a region of memory that is not shareable with other masters, then how can the cache line have have "Shared Clean" or "Shared…
In the PL310 TRM, the definition of the CACHE_ID register define the RTL release as the lower bits of the register.
To translate this RTL to a revision information, it is stated that
"RTL release 0x9 denotes r3p3 code of the cache controller. See the Release…
Hi AXI-experts,
Does AX4 support burst sizes larger than the bus width?
Narrow transactions are allowed, but do wider transactions also work?
Best regards,
Robert
Hi, I'm a graduate student living in south Korea. I'm studying about AMBA 3.0 AXI.
Recently, i read "AMBA® AXI Protocol.pdf". but i have three questions about AXI after reading.
Register slice is described in AMBA 3.0 AXI.
"This makes…
Hi Experts,
Is there any general feature available in the cortex processors to realize the cache lines by DMA through AXI ?
I found some features like CCI module available to provide this feature in multi-core environment. Other than that, is it possible…
Hello everyone,
I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.
As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :
3.9.4 Error response
If a slave…
Hello Ashley,
I have couple of basic doubts w.r.t ACE-Lite Slave.
The AMBA spec for ACE-Lite says that " ACE-Lite is used by master components that do not have hardware coherent caches". But they can issue transactions…
Hello:
Suppose there are 2 masters(master0 and master1) and 2 slaves(slave0 and slave1) for AXI4. As AXI4 protocol has removed WID signal for write data channel，When slave0 has received wvaild which is pulled up afte slave0 has…
Hi,
in the AMBA/AXI Protocol specification, I read
There must be no combinatorial paths between input and output signals on both master and slave interfaces.
What signals, explicitly, may not have combinatorials between them?
Thanks in advance.
Hi,
Regarding the HGRANT signal have following queries
1) When Master has requested for the bus access; arbiter has provided it the grant; When the arbiter can pulls out the HGRANT
a) For Non-locked transfer: When another master requests for bus access;…
Hi,
As indicated in few previous answers (Link Given below) on the big-endian, I believe that the big-endian type in AHB-Lite Spec is BE32. And further the AHB5 Spec added another type of big-endian as BE8. Hence, the active byte lanes for a 32-bit big…
We are using this IP in our system to adapt two AHB with different clock domains. We would like additional info about the behaviour of it's HREADYOUTS signal. We are using it in the following scenario:
Hello....!!!
Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?
Hi ,
In AHB specs, There is one note as below.
Note
Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…
Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?
Hi All,
1) 1st master is doing locked write transfer to 'X location after that, Can 2nd master initiate a read normal transfer for 'Y address in same slave? . And still unlocked transfer is not initiated by the 1st master?.…
In ACE Specifications - ARM IHI 0022E, in ReadNoSnoop transactions how is the following other state of cacheline
given on page number C4-197 transaction permitted :
Start State - ShareClean
RRESP[3] - 0, RRESP[2] - 0
End State - Invalid or UniqueCl…
AXI4:what will happen if there is a AXI rd and wr concurrently for a same address for a particular slave??
In AXI, low-power mode uses CSYSREQ, CSYSACK and CACTIVE three signal to realize the function, but I think only CSYSREQ and CACTIVE can realize the fuctionk, CSYSACK seems to be unnecessary?
AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?
As usual, we talk about cache is mainly refer to the cache inside CPU, but AXI's cache or buffer…
