Can the AMBA AHB Slave give multiple SPLIT response again to the AHB Master that has been given SPLIT response before and after updating hsplit signal for that Master by the Slave?

Hello,

with reference to the subject above,

in ahb spec.,there are both HRDATA and HWDATA buses.

However,i can't figure out any possible scenario to meet the necessary of design instead of using same data bus.

Hope someone can give some comment,thanks…

Hi, I am looking for a memory controller for AHB, dual (or multi) channel.

I found one in the ARM site but for AXI.

Thank you

Hi,

    I have a scenario like 2masters firing write or read burst to different slave.

     M1 ---> S1 (Slave S1 performs SPLIT response for any transfer of the burst )

     M2 ---> S2 (Slave S2 performs SPLIT response…

Hi ,

In AHB specs, There is one note as below.

Note

Every slave must have a predetermined maximum number of wait states that it will insert before it backs off the bus, in order to allow the calculation of the latency of accessing the bus. It is recommended…

Hi,

   I have a question on AMBA AHB, Let us assume we are firing INCR4 burst from master M1.

  Let us assume  EBT is happened during 2nd transfer address phase of INCR4 burst (i.e Master M1 lost its grant without driving of its data phase and…

In AHB5, we have extended memory bits as [6:4] hprot. Previously we have [3:0] hprot. For implementation purpose, i treated [6:4] as a separate signal. This separate signal am qualifying based on some filter, just because not to consider for older AHB…

Hello....!!!

Can anyone tell the minimum and maximum frequency or bandwidth on which AMBA AHB, APB, AXI and CHI and ACE can work successfully?

i want to design a bridge between APB  and AHB in verilog

my design consists of :

1. control clock unit (ccu)   // using APB

2. my DUT contains registers module & functional module  // using AHB

3. tow memories (source memory and…

I have a problem about AHB 2.0, the circumstance is:

The master send two burst without IDLE transfer, and the HBURST is INCR.

So the arbiter can’t predict when the burst finishes.

And the sequence of the HTRANS is as below:

| NONSEQ  | SEQ | SEQ | SEQ…

I wanted to know the relation b/w HWRITE and HSEL

I am trying verify the bridge...........

I am working on ahb bridge , I am trying to sample address when hready is high .

               is it correct or not ?

Address is indepent of hready…

The spec simply states that a master may cancel a burst after receiving an ERROR response for one of its transfers or continue with the remaining transfers.

The spec does not go on to state what the slave is supposed to do in that case though. Should it…

Hello everyone,

Please describe me the transfer continuation process after ERROR response from the slave.

As shown in the above figure at cycle T4 if MASTER identifies the ERROR response from the SLAVE. Now, if the MASTER wants to continue the current transfer…

Hello everyone,

I want to understand the transfer continuation process from AHB MASTER during ERROR response from AHB SLAVE.

As specified in the AMBA Specifications (Rev 2.0) IHI0011A_AMBA_SPEC.pdf section 3.9.4 page no 3-23 :

3.9.4 Error response

If a slave…

Hi,

My question is about duration of hsel in AHB. While performing a write operation to a particular slave, if hsel for the slave is asserted (hsel=1) in the address
face and is deasserted (hsel=0) in the data phase, will it guarantee that data is written…

Hi there,

  Here is an AHB slave module which only supports word access (HSIZE[2:0] = 3'b010).

  I plan to put it in a SoC, in which masters and interconnect could  launch byte, half-word and word transcation.

  Till now, I have 2 ideas…