Hi all,
I'm trying to add the ARM compute library on Xiling SDK to run a CNN on the Cortex A-9. I'm having a hard time trying to integrate it. To begin with, i downloaded the ComputeLibrary master folder at https://github.com/ARM-software/Comp…
Hi all,
I'm trying to add the ARM compute library on Xiling SDK to run a CNN on the Cortex A-9. I'm having a hard time trying to integrate it. To begin with, i downloaded the ComputeLibrary master folder at https://github.com/ARM-software/Comp…
Dear,
I am developing projcet using cortex-A8, I optimize some algorithm code on cortex-A8 cpu.
The code shall be ported to cortex-A15 in near future, I got some information about BEON and VFP from website,the different NEON / VFP version betweem cortex…
According to the manual, we can select PMU events as external input resource of ETM. However, the manual does not describe it in detail, and my attempts also failed.
To perform the experiment, i configure the following registers,
TRCCONFIGR -> 0x18c1 …
Hello,
I have used DS-5+DSTREAM to connect to the A57/A53 big.LITTLE clusters on my Juno dev board. I use the startup_ARMv8_GICv2 example project included with DS-5 as the bare-metal image to run.
When I navigate to the cache view window in DS-5, I can…
Hey guys,
I need your help because I have to count the number of L2 instruction access, miss and hits. But in the data-sheet I did not find the events that I have to count.
I found it in the ARM V8 data-sheet. Therefore, is it usable on A72 & A53 even…
Hi everyone,
I am using ETM v3.3 and ETB11 on Cortex-A8 to trace the execution of the applications. As the size of the ETB is normally very limited on the development boards, it always overflow in less than 1ms. After the overflow, we may loss some important…
Hi all,
I am trying to use one Cortex-A57 (debugger) core to debug a Cortex-A53 core (target) on Juno board. According to the armv8 architecture manual, i may halt the the target and use EDITR instruction to force the target execute instructions. So,…
Hi there,
Is there any way from DS-5 development studio to access my host NIC ethernet card?
I want to write a bare metal code (Cortext A9), creating an ARP packet on DS-5 and I would like to test it if its working with my host NIC Card drivers.
Is it…
Hi all,
I am working with a simple sqrt kernel. Code given below at end of post. It calculates the sqrt on a given array and stores it into a new array.
However, when compiling with a gcc compiler as - gcc -mcpu=cortex-a53 -mfpu=neon neon_sqrt_kernel.…
Hi ,
Please I need help, I need to download Eclipse in My board DE1-Soc FPGA Which has the latest dual-core Cortex-A9 embedded cores with architecture armv7l and the other board Rasberry ARM Cortex-A53.
do you have any idea which packages can I install…
I am working on smp_prime code of ARM - A9. And a i want to use that code for cortex A7.
But after making changes like setting smp bit in ACTLR, Making the memory region device and non coherent- then if i enable the MMU bit from system control register…
Hi experts,
Recently, I'm trying to evaluate the code execution time when using the A53 core and the A57 core.
However, my result shows A53 core is much faster than the A57 core, which does not make sense to me so I want to share my case here to see…
Hello,
I'm developing a Baremetal application running on ARM Cortex A35 (ARMv8).
I have succeeded to enable the Caches and MMU in EL-1.
My questions are:
1. Can I enable the MMU and invalidate and enable the Caches in EL-2 without enabling them…
Counter-timer Physical Count register CNTPCT_EL0 always reads zero on FVP_Base_Cortex-A35x1.
I expect the value of this register to change over time.
I set $CNTFRQ_EL0=35000000, and $CNTP_CTL_EL0=5.
What is the possible reasons, and how is there any configuration…
Hello,
I am not sure whether this is a right but I thought to give it a go as I am cross compiling snort for an ARM-based system.
I am very new to cross-compilation using ptxdist tool. I am using ptxdist version 2013.03.0 and trying to build snort 2.9…
Hi all,
I am trying to use the ETM on iMX53 qsb, which contains a Cortex-A8 processor. In the board, the trace result of the ETM is outputted to both ETB and TPIU via an ATB replicator, looks like the following figure,

I am going to enable the ETM and…
Hi,
I am trying to compile PMU Cycle Counter as per the code available in this blog PMU Enable on a RPI3 B+ using Suse 64 bits Aarch 64 4.12.14-lp150.12.28-default.
I have the Assembly error on each MRC or MCR instructions. In the ARM i have the feeling…
Hi,
I am getting below mentioned error when kernel is trying to mount Big endian NFS root filesystem.
[ 9.091012] devtmpfs: mounted
[ 9.094985] Freeing unused kernel memory: 1024K
[ 9.114876] init (1): undefined instruction: pc=b6fce0a8
[ 9.120227] CPU…
I was talking with a colleague who is a specialist on KVM about having Android and Ubuntu on the Chromebook.
If you have a Chromebook using Samsung Exynos 5 SoC and you want to use virtualization to run a couple of operating systems:
I had a hobby where I enjoyed it very much when I had stress it is programming on assembler. I want to have some fun programming my ARM A9. Im using android OS. I wonder maybe any of you can guide me how to do this on android? And is there any free tools…
Compiler options is one of those subjects that can get decidedly more complicated as you descend the rabbit hole. Undoubtedly, developers using or creating C/C++/Assembly libraries in Android are seeking to compile the most optimal binary for as many…
I expect to have a Rockchip RK3288-based system, (quad-core Cortex-A17's), which comes pre-loaded with KitKat. Is there any documentation on whether, and if so, how I could build a Linux system around the same kernel, so as to create a dual-boot Android…