AXI write strobes

Note: This was originally posted on 21st February 2007 at http://forums.arm.com the AXI spec says: 10.1 About unaligned transfers [...] For any burst that is made up of data transfers wider than one byte...
AXI write strobes

Note: This was originally posted on 21st February 2007 at http://forums.arm.com the AXI spec says: 10.1 About unaligned transfers [...] For any burst that is made up of data transfers wider than one byte...
AXI Write Strobe for Unaligned Address

Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
AXI Write Strobe for Unaligned Address

Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
How should AXI slave handle with illegal write strobe.

Does the AXI slave need to report the illegal write strobe from master or always assuming the write strobe is correct? Should AXI slave ignore the remaining burst after it detecting an illegal write strobe...