early burst termination - ahb - interconnect

the system have 2 masters - M0,M1, and 2 slaves- S0, S1. M0 transmit to S0, INCR4 : NON,SEQ and then early burst termination and M1 transmit to S1 new burst. In that clock cycle what S0 expects to see...
Burst termination with BUSY on AHB Lite

Hello, I have some question when Master used "Undefined Length" and termination with BUSY, the following is my waveform : My question is : 1) When T5-T6, Slave still on address phase? 2) When...
Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
Burst termination with BUSY transfer on AHB

I heard that when HTRANS is BUSY, undefined length burst (INCR) will be terminated. But when I read a document, I saw an example that BUSY transfer followed by SEQ transfer during an undefined length...
Burst termination with BUSY on AHB Lite

Hello, I have some question when Master used "Undefined Length" and termination with BUSY, the following is my waveform : My question is : 1) When T5-T6, Slave still on address phase? 2) When...