• CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...
  • CHI protocol cache line states
    The CHI protocol spec mentions 2 additional cache line states as compared to AXI viz., Unique Clean Empty and Unique Dirty Partial. What is the reason for introducing two additional cache line states...
  • ReadClean transaction (ACE protocol)
    Hello everyone, Can any one explain me why there is a case where a start state in Unique Dirty leads to a final state in Unique Dirty for a readClean transaction in ACE protocol. This transaction requires...
  • ReadClean transaction (ACE protocol)
    Hello everyone, Can any one explain me why there is a case where a start state in Unique Dirty leads to a final state in Unique Dirty for a readClean transaction in ACE protocol. This transaction requires...
  • Should the Data value be 0 when corresponding BE is 0 in Arm CHI E Spec?
    In Chapter 2.10.3 Byte Enables, does the following description mean that "the Data value must be 0 when corresponding BE is 0"?