ARMv8 AArch64: trapping hardware breakpoint to EL2

Hi everyone! I want to set and then trap EL1 hardware breakpoints to EL2. I didn't perfectly understand if such an action is possible at all. In some places the documentation said that MDCR_EL2.TDE...
ARMv8 AArch64: trapping hardware breakpoint to EL2

Hi everyone! I want to set and then trap EL1 hardware breakpoints to EL2. I didn't perfectly understand if such an action is possible at all. In some places the documentation said that MDCR_EL2.TDE...
ARMv8-A Trap access of EL2 TTBR to EL3

Hi all, I want to trap the non-secure access of several system registers (TTBR0_EL2, VTTBR_EL2, HCR_EL2, etc.) to EL3. However, when I look up the ARMv8-A reference manual, I cannot find some useful...
ARMv8-A Trap access of EL2 TTBR to EL3

Hi all, I want to trap the non-secure access of several system registers (TTBR0_EL2, VTTBR_EL2, HCR_EL2, etc.) to EL3. However, when I look up the ARMv8-A reference manual, I cannot find some useful...
Armv8-R AEM FVP exclusive monitor breaks when cache_state_modelled=0

I'm running a simple bare-metal application on Armv8-R AEM FVP (FVP_BaseR_AEMv8R 11.20.15). For the same exact code on the model's Armv8-A counterpart (FVP_Base_RevC-2xAEMvA), I noticed that setting cache_state_modelled...