Import SOC design in eclipse

I have design SOC in system canvas . its build successfully on ISIM and cadi target but when I import in DS Eclipse it shows error I am adding.exe file
SoC FPGA design to ASIC

Hey! Has anyone got any experience (I'm not entirely sure if its possible) in moving from an SoC FPGA design to an ASIC? I know you can go from FPGA rtl / netlist to an ASIC but what about the SoC part...
Import SOC design in eclipse

I have design SOC in system canvas . its build successfully on ISIM and cadi target but when I import in DS Eclipse it shows error I am adding.exe file
SoC FPGA design to ASIC

Hey! Has anyone got any experience (I'm not entirely sure if its possible) in moving from an SoC FPGA design to an ASIC? I know you can go from FPGA rtl / netlist to an ASIC but what about the SoC part...
How to Design secure boot on ARM based SoC?

I have started working on TI's ARM based Soc and wanted to know how to design secure boot ? Is implementation of Secure boot is part of first stage boot-loader Rom boot loader ? I have gone through the...