• AHB DeadLock: HREADY=0 & HTRANS=BUSY
    If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition...
  • AHB DeadLock: HREADY=0 & HTRANS=BUSY
    If the slave asserts wait state (HREADY=0), and master asserts HTRANS =BUSY, then should the slave wait for change of HTRANS from BUSY to NONSEQ/SEQ or should the slave change the HREADY=1. This condition...
  • AHB HREADY low not after address phase
    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles. Thanks
  • AHB HREADY low not after address phase
    What would happen if HREADY will be lower not after address phase, but according to HW internal logic that wants to hold CPU for some clock cycles. Thanks
  • AHB5: performing a burst transfer with HBURST=SINGLE and HTRANS=NONSEQ.
    Greetings, all! So, I have two questions about the AHB5 protocol: (1) I see there are two ways of performing an undefined length burst transfer using AHB5 protocol: (1.1) Set HBURST = INCR and HTRANS...