Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?

Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example. Bus width and data transfer width should be both 32 bits. First write should be...
Does an AXI4 master have to assert the correct WSTRB for unaligned transfers?

Take the unaligned transfer on page A3-55 in the "AMBA AXI and ACE Protocol Specification" with address 0x07 as example. Bus width and data transfer width should be both 32 bits. First write should be...
AXI4: Unaligned read transactions

Hi guys, I'm new to the AXI ecosystem. However, I have one question related to unaligned read transfers. Does AXI4 support unaligned read transfers although er are no strobe lines? If so, which data on...
AXI4: Unaligned read transactions

Hi guys, I'm new to the AXI ecosystem. However, I have one question related to unaligned read transfers. Does AXI4 support unaligned read transfers although er are no strobe lines? If so, which data on...
Why AWLEN signal is optional for master and required for slave in AXI4 protocol ?

Why AWLEN signal is optional for master in AXI4 protocol ? If it is optional for master then how slave will get that signal because it is required for slave ?