AXI Master dependencies between xREADY and xVALID on different transactions

Hi, The AXI spec notes the dependencies between xREADY and xVALID for a Master as follows: the master must not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or WVALID ...
AXI Master dependencies between xREADY and xVALID on different transactions

Hi, The AXI spec notes the dependencies between xREADY and xVALID for a Master as follows: the master must not wait for the slave to assert AWREADY or WREADY before asserting AWVALID or WVALID ...
AXI 4 protocol - can read transaction and write transaction occur at the same time?

AXI 4 protocol - can read transaction and write transaction occur at the same time? In addition can 2 or more wrirte transacation occur at the same time?
AXI 4 protocol - can read transaction and write transaction occur at the same time?

AXI 4 protocol - can read transaction and write transaction occur at the same time? In addition can 2 or more wrirte transacation occur at the same time?
Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction

Hello All, I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address. When I read back at the same address, I am getting as 2 64 bit data...