• AXI FIXED burst ; Wr/Rd narrow transactions.
    1. I'm examining AXI burst of FIXED type. 2. Data bus width is of 128bit. 3. case scenario WRITE :     awlen    = 2 (3 write transfers)     awsize  = 2 (32bit per each transfer)     awburst = 0 (FIXED...
  • AXI FIXED burst ; Wr/Rd narrow transactions.
    1. I'm examining AXI burst of FIXED type. 2. Data bus width is of 128bit. 3. case scenario WRITE :     awlen    = 2 (3 write transfers)     awsize  = 2 (32bit per each transfer)     awburst = 0 (FIXED...
  • Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction
    Hello All, I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address. When I read back at the same address, I am getting as 2 64 bit data...
  • Narrow burst (32 bit read) on a 64 bit data bus AXI read transaction
    Hello All, I have a 64 bit data bus and I am making a 32 bit INCR with length 4(INCR4) write on it by giving the starting address. When I read back at the same address, I am getting as 2 64 bit data...
  • [AXI protocol] Is a master allowed to disable byte lanes in a non-narrow WRAP burst?
    Hello, A couple of further details on the question. Let's assume that I have a 64-bit data bus and a 32-bit address bus. A master issues a WRAP burst with AWADDR[31:0] = 32'd8 and AWSIZE[2:0]...