AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache? As usual, we talk about cache is mainly refer...
AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache?

AMBA AXI can set data transfer cacheable or bufferable, I want ask this cache or buffer refer to the cache or buffer inside AXI interconnect or system cache? As usual, we talk about cache is mainly refer...
how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"?

ARMv8 introduces this new attribute of memory type. (B2.8.2) And also it recommends that "early write acknowledgement" attribute should be exported to interface between PE and interconnect fabric. ...
how "Early Write Acknowledgement" is encoded on AXI AxCache ? equal to "bufferable"?

ARMv8 introduces this new attribute of memory type. (B2.8.2) And also it recommends that "early write acknowledgement" attribute should be exported to interface between PE and interconnect fabric. ...
Regarding mismatched memory attributes and cacheability

As described in ARM ARM (ARMv7), mismatched memory attributes for mapping a physical region would happen when either/all of the memory type, shareability or cacheability of aliases differ My question...