• AXI Write Strobe for Unaligned Address
    Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
  • AXI Write Strobe for Unaligned Address
    Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
  • why we need write strobe in axi
    why we need write strobe signal in axi where we generate in our verif env Thanks
  • why we need write strobe in axi
    why we need write strobe signal in axi where we generate in our verif env Thanks
  • How should AXI slave handle with illegal write strobe.
    Does the AXI slave need to report the illegal write strobe from master or always assuming the write strobe is correct? Should AXI slave ignore the remaining burst after it detecting an illegal write strobe...