AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

Hi guys, I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus. First consider an unaligned access on address 0x1. Can this access be created in 2 ways? 1) Addr...
AXI4: Write-Alignemnent modes? Partial writing with write strobes possible?

Hi guys, I have two questions related to the write-strobing in AXI4. Both examples work on a 32-bit bus. First consider an unaligned access on address 0x1. Can this access be created in 2 ways? 1) Addr...
AXI Write Strobe for Unaligned Address

Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
AXI Write Strobe for Unaligned Address

Hello Forum, An AXI manager when transacting on a 256-bits wide data bus, issues the following transaction on the write address channel: address width: 32 data width : 256 awaddr: 32'h8C00_101b...
AXI write strobes

Note: This was originally posted on 21st February 2007 at http://forums.arm.com the AXI spec says: 10.1 About unaligned transfers [...] For any burst that is made up of data transfers wider than one byte...