How to know L2 cache ECC single / multiple bit error separately ?

For Cortex A53, I can't find separate bit definition for L2 ECC single and multiple bit error in L2MERRSR.... 1. bit 31 for L2MERRSR (L2MERRSR_EL1) is for L2 cache ECC multiple bit error, correct...
How to know L2 cache ECC single / multiple bit error separately ?

For Cortex A53, I can't find separate bit definition for L2 ECC single and multiple bit error in L2MERRSR.... 1. bit 31 for L2MERRSR (L2MERRSR_EL1) is for L2 cache ECC multiple bit error, correct...
Linking (joining/including) separate asm modules into 1 file

Hello All, i wanted to apply some modular approach in my program designing, so i decided to pre-write some common modules which are frequently used by me (like a customizable 7 segment display code...
Linking (joining/including) separate asm modules into 1 file

Hello All, i wanted to apply some modular approach in my program designing, so i decided to pre-write some common modules which are frequently used by me (like a customizable 7 segment display code...
Programming Multiple Targets with Multiple Eval Boards

Our application uses multiple target boards (with Luminary Micro Cortex-M3s) interconnected via a CAN bus. We're using a Luminary Micro eval board for programming them individually (with uVision4 via...