Cortex-A8 : instruction fetch for dual-issue

Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard to reason why...
Cortex-A8 : instruction fetch for dual-issue

Hi, We experiment the following loop code (runs 4096 iterations) and we get CPI=0.66 (in other words, loop initiation interval (II) is about 6 machine cycles). We are trying really hard to reason why...
unaligned data fetch in Cortexa9

I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
unaligned data fetch in Cortexa9

I have a question related to data fetch, when on gdb debugger I do an address read say as: X 0x81000000 Then it will fetch 64 bits as you told in reference to Cortex A9 If further I do X 0x81000004 Will...
Speculative data fetching on ARMv7-M

I am working with an ARMv7-M with a cache and trying to workout how the Speculative data fetching works or at least understand it. The only documentation I can find for it is a small section in ARM...