Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data

Hi there, good morning. I am using TMC as Embedded Trace Fifo and testing it for FULL condition. Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF? So...
Embedded Trace Fifo(ETF) in Hardware FIFO mode flushing trace data

Hi there, good morning. I am using TMC as Embedded Trace Fifo and testing it for FULL condition. Is there any way, I can stop TMC from not reading the trace data that is written in the SRAM of ETF? So...
fifo()

Hi All,, The Data is serially coming into my controller , is processed there and then sent out serially. The data is packed between header (8 zero bytes) and tailer (8 0xff bytes). Should i detect...
fifo()

Hi All,, The Data is serially coming into my controller , is processed there and then sent out serially. The data is packed between header (8 zero bytes) and tailer (8 0xff bytes). Should i detect...
UART FIFO

Hi, i got a problem with the UARTn FIFO . Can someone explain me how i get the data from this register? The manual says that, if i enable the Rx trigger level for example level3 (8 character) the...