• oregano 8051 core
    In the oregano 8051 architecture, at reset PC starts at address zero, can anybody tell me what to modify in the startup.a51 and init.a51 files, so that they correctly jump to address of main program...
  • oregano 8051 core
    In the oregano 8051 architecture, at reset PC starts at address zero, can anybody tell me what to modify in the startup.a51 and init.a51 files, so that they correctly jump to address of main program...
  • oregano 8051 parameterization test on FPGA
    has anybody here worked with the oregano systems 8051 ip core. I need help testing the parameterized number of timers on fpga. the lines from the user guide document are here: "In the VHDL source...
  • oregano 8051 parameterization test on FPGA
    has anybody here worked with the oregano systems 8051 ip core. I need help testing the parameterized number of timers on fpga. the lines from the user guide document are here: "In the VHDL source...
  • Problem in setting duration between the pulses using interrupt
    Hi all, I'm getting a set of variable frequency, and when I set the duration for the different time like 1hr,2hr etc the frequency and time runs and stops, for the given time. But the frequency...