Arm Musca A1 - SRAM0 MPC Security attribute during boot

Hi all, I am using Arm Musca-A1 in a project and I'm getting a strange behavior on the MPC connected to the internal SRAM0. During boot, I am loading some data to SRAM0 (S region). While when I access...
Arm Musca A1 - SRAM0 MPC Security attribute during boot

Hi all, I am using Arm Musca-A1 in a project and I'm getting a strange behavior on the MPC connected to the internal SRAM0. During boot, I am loading some data to SRAM0 (S region). While when I access...
Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map.

This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .
Can secure accesses access both secure and nonsecure address map, whereas, nonsecure only access nonsecure part of the address map.

This question was raised in the ' How to implement a secure IoT system on ARMv8-M ' webinar, view all the questions in the round up blog post .
Are simultaneous accesses to both ITCM and DTCM of Cortex-M7 possible?

Hi experts and ARM designers, I have found "ARM® Cortex®-M7 Processor Technical Reference Manual Revision r0p2" on the ARM site. By reading it I have a question. "Figure 1-3 Cortex-M7 functional diagram...