Stupid question

Ok be nice, this is my first time using a uP. For the XC167 eval board, the (256k x 16bit)SRAM memory is setup like this. The xc167 A18 through A1 goto A17-A0 on the memory, and the 167 A0 goes to L...
Stupid question

Ok be nice, this is my first time using a uP. For the XC167 eval board, the (256k x 16bit)SRAM memory is setup like this. The xc167 A18 through A1 goto A17-A0 on the memory, and the 167 A0 goes to L...
Still more stupid questions on Cortex-A7 instruction set

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found an answer to in ARMv7-A/R ARM Issue C. How is this special? LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD...
Still more stupid questions on Cortex-A7 instruction set

I've beem constructing a list of Cortex-A7 ARM-instructions, and there are some questions I haven't found an answer to in ARMv7-A/R ARM Issue C. How is this special? LDRD<c>_<Rt>,_<Rt2>,_<label>_LDRD...
a few questions regarding cygnal components

hi, im using keil ver. 2.38a, c51 compiler ver. 7.06, the cygnal 80c51f124 and i have a few questions regarding the cygnal components: 1. when debugging code larger than 32k, there seems to be a...