when overlays used , debugger shows wrong code when breakpoint is hit

Hello, for performance reasons I execute some code in internal SRAM (Controller: LPC54618) instead of flash. I need different functions at differtent times, so I use overlays to put the required function...
Calculating L1 hit latency and L2 hit latency

Note: This was originally posted on 16th January 2012 at http://forums.arm.com All, I am new here. I was interested in measuring the L1 hit latency for A15/A9. Which signals do I need to probe inside...
Calculating L1 hit latency and L2 hit latency

Note: This was originally posted on 16th January 2012 at http://forums.arm.com All, I am new here. I was interested in measuring the L1 hit latency for A15/A9. Which signals do I need to probe inside...
Will an outer non-cachable-write invalidate cacheline when hit in l2cache, with shared override bit set

A9, PL310 controller
CPU utilization is always 100% !

Hello all, I am writing an RTOS for an XC167 (just for fun, believe it or not :-) ). while running it on the Keil IDE I constantly experience 100% CPU usage. I wrote a preemptive scheduler with a task...