What is best practice for ARM compiler 6.7

I've been playing around with the ARM C compiler 6.6 and 6.7 for cortex m3 and I was wondering what is the best practice for the enabling of compiler warnings? What level of warnings should be a minimum...
What is best practice for ARM compiler 6.7

I've been playing around with the ARM C compiler 6.6 and 6.7 for cortex m3 and I was wondering what is the best practice for the enabling of compiler warnings? What level of warnings should be a minimum...
Text section size for executable created with ARMCC 6.7 is more than expected

Hi, I am porting Xilinx standalone drivers and libraries to armcc 6.7 compiler. I tried xilinx hello world application with the ported code base (for cortexa53 processor), and obseverd that text section...
Text section size for executable created with ARMCC 6.7 is more than expected

Hi, I am porting Xilinx standalone drivers and libraries to armcc 6.7 compiler. I tried xilinx hello world application with the ported code base (for cortexa53 processor), and obseverd that text section...
?CCASE bugs in optimize(9,size)

Version 5.1 C51.exe generates code that randomly resets when compiled optimized level 9, favor size, unless all switch statements are replaced with if-then. This is on years-old stable code that recently...